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authorDan Williams <dan.j.williams@intel.com>2009-09-09 04:42:53 +0400
committerDan Williams <dan.j.williams@intel.com>2009-09-09 04:42:53 +0400
commit128f2d567f906d38b11d993d8d97b9b988848e26 (patch)
tree523fd4b737bd44bccddb2425ae0b16f78a819e19 /drivers/dma
parent83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7 (diff)
downloadlinux-128f2d567f906d38b11d993d8d97b9b988848e26.tar.xz
ioat2+: add fence support
In preparation for adding more operation types to the ioat3 path the driver needs to honor the DMA_PREP_FENCE flag. For example the async_tx api will hand xor->memcpy->xor chains to the driver with the 'fence' flag set on the first xor and the memcpy operation. This flag in turn sets the 'fence' flag in the descriptor control field telling the hardware that future descriptors in the chain depend on the result of the current descriptor, so wait for all writes to complete before starting the next operation. Note that ioat1 does not prefetch the descriptor chain, so does not require/support fenced operations. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/ioat/dma_v2.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c
index 460b77301332..568923c5ddec 100644
--- a/drivers/dma/ioat/dma_v2.c
+++ b/drivers/dma/ioat/dma_v2.c
@@ -710,6 +710,7 @@ ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
desc->txd.flags = flags;
desc->len = total_len;
hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
+ hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
hw->ctl_f.compl_write = 1;
dump_desc_dbg(ioat, desc);
/* we leave the channel locked to ensure in order submission */