diff options
| author | Martin Sperl <kernel@martin.sperl.org> | 2016-02-29 14:39:17 +0300 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2016-03-17 20:42:17 +0300 |
| commit | 6727f086cfe4ddcc651eb2bf4301abfcf619be06 (patch) | |
| tree | e4d3188411c381e2c41cbf42b4ad8a0a6f728b4f /drivers/clk | |
| parent | 4d3ac6662452060721599a3392bc2f524af984cb (diff) | |
| download | linux-6727f086cfe4ddcc651eb2bf4301abfcf619be06.tar.xz | |
clk: bcm2835: pll_off should only update CM_PLL_ANARST
bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
register, which may lose the other bits that are currently set by the
clock dividers.
It also now locks during the read/modify/write cycle of both
registers.
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
audio domain clocks")
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/bcm/clk-bcm2835.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index c74ed3fd496d..adbaa55e939c 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -910,8 +910,14 @@ static void bcm2835_pll_off(struct clk_hw *hw) struct bcm2835_cprman *cprman = pll->cprman; const struct bcm2835_pll_data *data = pll->data; - cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST); - cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN); + spin_lock(&cprman->regs_lock); + cprman_write(cprman, data->cm_ctrl_reg, + cprman_read(cprman, data->cm_ctrl_reg) | + CM_PLL_ANARST); + cprman_write(cprman, data->a2w_ctrl_reg, + cprman_read(cprman, data->a2w_ctrl_reg) | + A2W_PLL_CTRL_PWRDN); + spin_unlock(&cprman->regs_lock); } static int bcm2835_pll_on(struct clk_hw *hw) |