diff options
| author | Rhyland Klein <rklein@nvidia.com> | 2015-06-19 00:28:29 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-12-17 15:37:53 +0300 |
| commit | 6929715cf6b944d8f88beb2aa25658084de106ab (patch) | |
| tree | d2115c728dc40f5430acd8827c9b9af00f8bab2c /drivers/clk/tegra/clk.h | |
| parent | dd322f047d226a1134775c77c1c6088271d5d1de (diff) | |
| download | linux-6929715cf6b944d8f88beb2aa25658084de106ab.tar.xz | |
clk: tegra: pll: Add support for PLLMB for Tegra210
Tegra210 SoC's have 2 PLLs for memory usage. Add plumbing to register
and handle PLLMB.
PLLMB is used to allow switching between 2 PLLM's without having to use
and intermediate backup PLL, as we need to lock the PLL before we can
switch to it.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 97a5d712fe41..8724dc245f68 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -225,6 +225,8 @@ struct div_nmp { * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv * it may be more accurate (especially if SDM present) + * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This + * flag indicated that it is PLLMB. */ struct tegra_clk_pll_params { unsigned long input_min; @@ -281,6 +283,7 @@ struct tegra_clk_pll_params { #define TEGRA_PLL_BYPASS BIT(9) #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) #define TEGRA_MDIV_NEW BIT(11) +#define TEGRA_PLLMB BIT(12) /** * struct tegra_clk_pll - Tegra PLL clock @@ -387,6 +390,12 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); +struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, + void __iomem *clk_base, void __iomem *pmc, + unsigned long flags, + struct tegra_clk_pll_params *pll_params, + spinlock_t *lock); + /** * struct tegra_clk_pll_out - PLL divider down clock * |