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| author | Stephen Boyd <sboyd@codeaurora.org> | 2017-08-24 01:39:58 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-08-24 01:39:58 +0300 |
| commit | 535b1100d169589f095165c75918ad398943cc76 (patch) | |
| tree | a368f726bd4a1291fc45b12b8ac2d40aaee6f281 /drivers/clk/socfpga | |
| parent | 1dfcfa721f9390ed5fd1e9c48e9fd6e8208a4963 (diff) | |
| parent | c29f82951b974f27e0bc4ce2525db164f86f2e4d (diff) | |
| download | linux-535b1100d169589f095165c75918ad398943cc76.tar.xz | |
Merge tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
* Add more module clocks for R-Car V2H and M3-W,
* Add support for the R-Car Gen3 USB 2.0 clock selector PHY,
* Add support for the new R-Car D3 SoC,
* Allow compile-testing of all (sub)drivers now all dummy infrastructure
is available,
* Small fixes and cleanups.
* tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a7796: Add USB3.0 clock
clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY
clk: renesas: cpg-mssr: Add R8A77995 support
clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks
clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
clk: renesas: Add r8a77995 CPG Core Clock Definitions
clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table
clk: renesas: rcar-gen3-cpg: Drop superfluous variable
clk: renesas: Allow compile-testing of all (sub)drivers
clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks
clk: renesas: div6: Document fields used for parent selection
Diffstat (limited to 'drivers/clk/socfpga')
0 files changed, 0 insertions, 0 deletions