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| author | Duc Dang <dhdang@apm.com> | 2016-06-21 04:26:35 +0300 |
|---|---|---|
| committer | Duc Dang <dhdang@apm.com> | 2016-06-21 04:26:35 +0300 |
| commit | f0a78909bd6fc48c50d6557bac95a589d2f987d4 (patch) | |
| tree | e7ea986eca63316faba6002d14cd673fe441f2cd /arch | |
| parent | 0e999c79c0a0128abcdbf58b4d0802ad4410bfb9 (diff) | |
| download | linux-f0a78909bd6fc48c50d6557bac95a589d2f987d4.tar.xz | |
arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC
Correct X-Gene 2 timer interrupt polarity as low-level triggered.
Signed-off-by: Duc Dang <dhdang@apm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index e5ced2acb446..21028b145d91 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -198,10 +198,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 0 0xff04>, /* Secure Phys IRQ */ - <1 13 0xff04>, /* Non-secure Phys IRQ */ - <1 14 0xff04>, /* Virt IRQ */ - <1 15 0xff04>; /* Hyp IRQ */ + interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ + <1 13 0xff08>, /* Non-secure Phys IRQ */ + <1 14 0xff08>, /* Virt IRQ */ + <1 15 0xff08>; /* Hyp IRQ */ clock-frequency = <50000000>; }; |