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| author | Maarten ter Huurne <maarten@treewalker.org> | 2018-01-16 18:48:02 +0300 |
|---|---|---|
| committer | James Hogan <jhogan@kernel.org> | 2018-01-19 01:07:44 +0300 |
| commit | 1f7412e0e2f327fe7dc5a0c2fc36d7b319d05d47 (patch) | |
| tree | 4c23bb82d1a4562f96fceb49b1dffa90e12ce6a6 /arch | |
| parent | 9be5f3e92ed5a4176bb4d99b498dc87aaafa622b (diff) | |
| download | linux-1f7412e0e2f327fe7dc5a0c2fc36d7b319d05d47.tar.xz | |
MIPS: JZ4770: Work around config2 misreporting associativity
According to config2, the associativity would be 5-ways, but the
documentation states 4-ways, which also matches the documented
L2 cache size of 256 kB.
Signed-off-by: Maarten ter Huurne <maarten@treewalker.org>
Reviewed-by: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18488/
Signed-off-by: James Hogan <jhogan@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/mm/sc-mips.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 548acb7f8557..394673991bab 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -16,6 +16,7 @@ #include <asm/mmu_context.h> #include <asm/r4kcache.h> #include <asm/mips-cps.h> +#include <asm/bootinfo.h> /* * MIPS32/MIPS64 L2 cache handling @@ -220,6 +221,14 @@ static inline int __init mips_sc_probe(void) else return 0; + /* + * According to config2 it would be 5-ways, but that is contradicted + * by all documentation. + */ + if (current_cpu_type() == CPU_JZRISC && + mips_machtype == MACH_INGENIC_JZ4770) + c->scache.ways = 4; + c->scache.waysize = c->scache.sets * c->scache.linesz; c->scache.waybit = __ffs(c->scache.waysize); |