diff options
| author | Sonic Zhang <sonic.zhang@analog.com> | 2009-01-07 18:14:38 +0300 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2009-01-07 18:14:38 +0300 |
| commit | 4934540d9fd49c13dd1fbef640fcdad75e9a3329 (patch) | |
| tree | 759ac5af456bf0f17390b2420f45a7b9bfbc0d17 /arch | |
| parent | 501674a593e7cffc416bc15c99ed9589316406d8 (diff) | |
| download | linux-4934540d9fd49c13dd1fbef640fcdad75e9a3329.tar.xz | |
Blackfin arch: enable reprogram cclk and sclk for bf518f-ezbrd
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/blackfin/Kconfig | 5 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/mem_init.h | 6 |
2 files changed, 9 insertions, 2 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 56ee44d7b2d9..a949c4fbbddd 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -330,6 +330,11 @@ config MEM_MT48LC32M16A2TG_75 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) default y +config MEM_MT48LC32M8A2_75 + bool + depends on (BFIN518F_EZBRD) + default y + source "arch/blackfin/mach-bf518/Kconfig" source "arch/blackfin/mach-bf527/Kconfig" source "arch/blackfin/mach-bf533/Kconfig" diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h index 3cbc0f81ebf3..255a9316ad36 100644 --- a/arch/blackfin/include/asm/mem_init.h +++ b/arch/blackfin/include/asm/mem_init.h @@ -13,7 +13,8 @@ defined(CONFIG_MEM_GENERIC_BOARD) || \ defined(CONFIG_MEM_MT48LC32M8A2_75) || \ defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \ - defined(CONFIG_MEM_MT48LC32M16A2TG_75) + defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ + defined(CONFIG_MEM_MT48LC32M8A2_75) #if (CONFIG_SCLK_HZ > 119402985) #define SDRAM_tRP TRP_2 #define SDRAM_tRP_num 2 @@ -100,7 +101,8 @@ defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ defined(CONFIG_MEM_GENERIC_BOARD) || \ defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ - defined(CONFIG_MEM_MT48LC16M16A2TG_75) + defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ + defined(CONFIG_MEM_MT48LC32M8A2_75) /*SDRAM INFORMATION: */ #define SDRAM_Tref 64 /* Refresh period in milliseconds */ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ |