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| author | Kirill A. Shutemov <kirill@shutemov.name> | 2009-09-15 13:23:53 +0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-09-16 01:06:38 +0400 |
| commit | 910a17e57ab6cd22b300bde4ce5f633f175c7ccd (patch) | |
| tree | 2a1dea95ca2d50192216500d90d9b0358af1dc1d /arch | |
| parent | 59fcf48fdebe65e4774d2c7ec76b7845d281749a (diff) | |
| download | linux-910a17e57ab6cd22b300bde4ce5f633f175c7ccd.tar.xz | |
ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size
Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
It's not true at least for CPUs based on Cortex-A8.
List of CPUs with cache line size != 32 should be expanded later.
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/cache.h | 2 | ||||
| -rw-r--r-- | arch/arm/mm/Kconfig | 5 |
2 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index feaa75f0013e..66c160b8547f 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -4,7 +4,7 @@ #ifndef __ASMARM_CACHE_H #define __ASMARM_CACHE_H -#define L1_CACHE_SHIFT 5 +#define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /* diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 5fe595aeba69..8d43e58f9244 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -771,3 +771,8 @@ config CACHE_XSC3L2 select OUTER_CACHE help This option enables the L2 cache on XScale3. + +config ARM_L1_CACHE_SHIFT + int + default 6 if ARCH_OMAP3 + default 5 |