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| author | GuanXuetao <gxt@mprc.pku.edu.cn> | 2011-02-26 16:21:18 +0300 |
|---|---|---|
| committer | GuanXuetao <gxt@mprc.pku.edu.cn> | 2011-03-17 04:19:19 +0300 |
| commit | e5abf78b57199a417eb01ff922a5ea6ff9e10b61 (patch) | |
| tree | 6f72a13d44c0dc8c4d575d84885f5694c16ed1da /arch/unicore32/kernel/clock.c | |
| parent | 4517366d870b89d6fb8c0c90deb6c73d975908af (diff) | |
| download | linux-e5abf78b57199a417eb01ff922a5ea6ff9e10b61.tar.xz | |
unicore32 io: redefine __REG(x) and re-use readl/writel funcs
-- by advice of Arnd Bergmann
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/unicore32/kernel/clock.c')
| -rw-r--r-- | arch/unicore32/kernel/clock.c | 34 |
1 files changed, 18 insertions, 16 deletions
diff --git a/arch/unicore32/kernel/clock.c b/arch/unicore32/kernel/clock.c index 80323db581fd..18d4563e6fa5 100644 --- a/arch/unicore32/kernel/clock.c +++ b/arch/unicore32/kernel/clock.c @@ -20,6 +20,7 @@ #include <linux/clk.h> #include <linux/mutex.h> #include <linux/delay.h> +#include <linux/io.h> #include <mach/hardware.h> @@ -152,28 +153,29 @@ int clk_set_rate(struct clk *clk, unsigned long rate) if (ret) return ret; - if (PM_PLLVGACFG == pll_vgacfg) + if (readl(PM_PLLVGACFG) == pll_vgacfg) return 0; /* set pll vga cfg reg. */ - PM_PLLVGACFG = pll_vgacfg; + writel(pll_vgacfg, PM_PLLVGACFG); - PM_PMCR = PM_PMCR_CFBVGA; - while ((PM_PLLDFCDONE & PM_PLLDFCDONE_VGADFC) + writel(PM_PMCR_CFBVGA, PM_PMCR); + while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_VGADFC) != PM_PLLDFCDONE_VGADFC) udelay(100); /* about 1ms */ /* set div cfg reg. */ - PM_PCGR |= PM_PCGR_VGACLK; + writel(readl(PM_PCGR) | PM_PCGR_VGACLK, PM_PCGR); - PM_DIVCFG = (PM_DIVCFG & ~PM_DIVCFG_VGACLK_MASK) - | PM_DIVCFG_VGACLK(pll_vgadiv); + writel((readl(PM_DIVCFG) & ~PM_DIVCFG_VGACLK_MASK) + | PM_DIVCFG_VGACLK(pll_vgadiv), PM_DIVCFG); - PM_SWRESET |= PM_SWRESET_VGADIV; - while ((PM_SWRESET & PM_SWRESET_VGADIV) == PM_SWRESET_VGADIV) + writel(readl(PM_SWRESET) | PM_SWRESET_VGADIV, PM_SWRESET); + while ((readl(PM_SWRESET) & PM_SWRESET_VGADIV) + == PM_SWRESET_VGADIV) udelay(100); /* 65536 bclk32, about 320us */ - PM_PCGR &= ~PM_PCGR_VGACLK; + writel(readl(PM_PCGR) & ~PM_PCGR_VGACLK, PM_PCGR); } #ifdef CONFIG_CPU_FREQ if (clk == &clk_mclk_clk) { @@ -323,15 +325,15 @@ struct { static int __init clk_init(void) { #ifdef CONFIG_PUV3_PM - u32 pllrate, divstatus = PM_DIVSTATUS; - u32 pcgr_val = PM_PCGR; + u32 pllrate, divstatus = readl(PM_DIVSTATUS); + u32 pcgr_val = readl(PM_PCGR); int i; pcgr_val |= PM_PCGR_BCLKMME | PM_PCGR_BCLKH264E | PM_PCGR_BCLKH264D | PM_PCGR_HECLK | PM_PCGR_HDCLK; - PM_PCGR = pcgr_val; + writel(pcgr_val, PM_PCGR); - pllrate = PM_PLLSYSSTATUS; + pllrate = readl(PM_PLLSYSSTATUS); /* lookup pmclk_table */ clk_mclk_clk.rate = 0; @@ -346,7 +348,7 @@ static int __init clk_init(void) clk_bclk32_clk.rate = clk_mclk_clk.rate / (((divstatus & 0x0000f000) >> 12) + 1); - pllrate = PM_PLLDDRSTATUS; + pllrate = readl(PM_PLLDDRSTATUS); /* lookup pddr_table */ clk_ddr_clk.rate = 0; @@ -357,7 +359,7 @@ static int __init clk_init(void) } } - pllrate = PM_PLLVGASTATUS; + pllrate = readl(PM_PLLVGASTATUS); /* lookup pvga_table */ clk_vga_clk.rate = 0; |