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| author | Paul Mundt <lethal@linux-sh.org> | 2006-11-05 10:48:42 +0300 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2006-12-06 04:45:37 +0300 |
| commit | 710ee0cc45d095f7697821b330a3f8280205c2be (patch) | |
| tree | 8bce794be73a6961d118d485c097232628812e94 /arch/sh/kernel/traps.c | |
| parent | f36af3fd377081d3ac2ff6b63a60f8db8b3bf531 (diff) | |
| download | linux-710ee0cc45d095f7697821b330a3f8280205c2be.tar.xz | |
sh: SE7206 build fixes.
A number of API changes happened underneath the 7206 patches, update
for everything that broke.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/traps.c')
| -rw-r--r-- | arch/sh/kernel/traps.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c index 1edec2709efe..f558748d7543 100644 --- a/arch/sh/kernel/traps.c +++ b/arch/sh/kernel/traps.c @@ -107,8 +107,6 @@ static inline void die_if_kernel(const char *str, struct pt_regs *regs, die(str, regs, err); } -static int handle_unaligned_notify_count = 10; - /* * try and fix up kernelspace address errors * - userspace errors just cause EFAULT to be returned, resulting in SEGV @@ -347,6 +345,13 @@ static inline int handle_unaligned_delayslot(struct pt_regs *regs) #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) +/* + * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit + * opcodes.. + */ +#ifndef CONFIG_CPU_SH2A +static int handle_unaligned_notify_count = 10; + static int handle_unaligned_access(u16 instruction, struct pt_regs *regs) { u_int rm; @@ -483,6 +488,7 @@ static int handle_unaligned_access(u16 instruction, struct pt_regs *regs) regs->pc += 2; return ret; } +#endif /* CONFIG_CPU_SH2A */ #ifdef CONFIG_CPU_HAS_SR_RB #define lookup_exception_vector(x) \ @@ -501,8 +507,10 @@ asmlinkage void do_address_error(struct pt_regs *regs, { unsigned long error_code = 0; mm_segment_t oldfs; +#ifndef CONFIG_CPU_SH2A u16 instruction; int tmp; +#endif /* Intentional ifdef */ #ifdef CONFIG_CPU_HAS_SR_RB |