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| author | Christophe Leroy <christophe.leroy@c-s.fr> | 2016-08-23 16:58:56 +0300 |
|---|---|---|
| committer | Scott Wood <oss@buserror.net> | 2016-09-25 10:38:53 +0300 |
| commit | 834e5a692120cc25c3935e8652a1989c2bc1c9e9 (patch) | |
| tree | 7b9707625fe89d567ceef4f6a8816807a3de5f3d /arch/powerpc/include/asm/reg_8xx.h | |
| parent | fff69fd03d1290297fcd039b07819fafa69ffc0a (diff) | |
| download | linux-834e5a692120cc25c3935e8652a1989c2bc1c9e9.tar.xz | |
powerpc/8xx: use SPRN_EIE and SPRN_EID to enable/disable interrupts
The 8xx has two special registers called EID (External Interrupt
Disable) and EIE (External Interrupt Enable) for clearing/setting
EE in MSR. It avoids the three instructions set mfmsr/ori/mtmsr or
mfmsr/rlwinm/mtmsr and it avoids using a general register.
We just have to write something in the special register to change MSR EE
bit. So we write r0 into the register, regardless of r0 value.
Writing to one of those two special registers also set the MSR RI bit,
but this bit is only unset during beginning of exception prolog and end
of exception epilog. When executing C-functions MSR RI is always set.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc/include/asm/reg_8xx.h')
| -rw-r--r-- | arch/powerpc/include/asm/reg_8xx.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_8xx.h b/arch/powerpc/include/asm/reg_8xx.h index 94d01f81e668..0197e12f7d48 100644 --- a/arch/powerpc/include/asm/reg_8xx.h +++ b/arch/powerpc/include/asm/reg_8xx.h @@ -25,6 +25,10 @@ #define SPRN_MD_RAM0 825 #define SPRN_MD_RAM1 826 +/* Special MSR manipulation registers */ +#define SPRN_EIE 80 /* External interrupt enable (EE=1, RI=1) */ +#define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */ + /* Commands. Only the first few are available to the instruction cache. */ #define IDC_ENABLE 0x02000000 /* Cache enable */ |