diff options
| author | James Hogan <james.hogan@imgtec.com> | 2017-03-14 13:25:45 +0300 |
|---|---|---|
| committer | James Hogan <james.hogan@imgtec.com> | 2017-03-28 17:36:17 +0300 |
| commit | 4fa9de5a645a9770679032a7eea0604f9a36eaf3 (patch) | |
| tree | 83d3672e5b49129a7843d0c093cd543fe0499994 /arch/mips/mm/cache.c | |
| parent | 7d8a528d19815e57566d1e2277f9535e43f4cb68 (diff) | |
| download | linux-4fa9de5a645a9770679032a7eea0604f9a36eaf3.tar.xz | |
KVM: MIPS/Emulate: Adapt T&E CACHE emulation for Octeon
Cache management is implemented separately for Cavium Octeon CPUs, so
r4k_blast_[id]cache aren't available. Instead for Octeon perform a local
icache flush using local_flush_icache_range(), and for other platforms
which don't use c-r4k.c use __flush_cache_all() / flush_icache_all().
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <david.daney@cavium.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Diffstat (limited to 'arch/mips/mm/cache.c')
| -rw-r--r-- | arch/mips/mm/cache.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 6db341347202..899e46279902 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -24,6 +24,7 @@ /* Cache operations. */ void (*flush_cache_all)(void); void (*__flush_cache_all)(void); +EXPORT_SYMBOL_GPL(__flush_cache_all); void (*flush_cache_mm)(struct mm_struct *mm); void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, unsigned long end); |