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authorKevin Cernekee <cernekee@gmail.com>2014-10-21 08:27:52 +0400
committerRalf Baechle <ralf@linux-mips.org>2014-11-24 09:45:10 +0300
commitbdb2e05c900d0c2a14605411dc054f284241d42e (patch)
treede867f32032648094369d30993955cf5c760e9ef /arch/mips/kernel/smp-bmips.c
parent3526f74fa925e44335b94ed0c9f93648e26058ef (diff)
downloadlinux-bdb2e05c900d0c2a14605411dc054f284241d42e.tar.xz
MIPS: BMIPS: Align secondary boot sequence with latest firmware releases
On some older BMIPS5200 (dual core / quad thread) platforms, the PROM code set up CPU2/CPU3 so they would be started through an NMI instead of through the ACTION register. But this was incompatible with some power management features that were later added, so the scheme was changed so that Linux is fully responsible for booting CPU2/CPU3. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8157/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/smp-bmips.c')
-rw-r--r--arch/mips/kernel/smp-bmips.c12
1 files changed, 1 insertions, 11 deletions
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 06bb5ed6d80a..4e569113ff56 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -213,17 +213,7 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
set_c0_brcm_cmt_ctrl(0x01);
break;
case CPU_BMIPS5000:
- if (cpu & 0x01)
- write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
- else {
- /*
- * core N thread 0 was already booted; just
- * pulse the NMI line
- */
- bmips_write_zscm_reg(0x210, 0xc0000000);
- udelay(10);
- bmips_write_zscm_reg(0x210, 0x00);
- }
+ write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
break;
}
cpumask_set_cpu(cpu, &bmips_booted_mask);