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author | Will Deacon <will.deacon@arm.com> | 2014-11-21 17:22:22 +0300 |
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committer | Will Deacon <will.deacon@arm.com> | 2014-11-21 17:22:22 +0300 |
commit | 7f73f7aef824b8bc27046edaf6b73bca4b0e7669 (patch) | |
tree | d1d9fe5dce6d67a52432f80dfe65b25b90693021 /arch/arm64/include/asm/cpufeature.h | |
parent | 1b907f46db07405b6676addb91b32c546d772fcd (diff) | |
download | linux-7f73f7aef824b8bc27046edaf6b73bca4b0e7669.tar.xz |
arm64: mm: report unhandled level-0 translation faults correctly
Translation faults that occur due to the input address being outside
of the address range mapped by the relevant base register are reported
as level 0 faults in ESR.DFSC.
If the faulting access cannot be resolved by the kernel (e.g. because
it is not mapped by a vma), then we report "input address range fault"
on the console. This was fine until we added support for 48-bit VAs,
which actually place PGDs at level 0 and can trigger faults for invalid
addresses that are within the range of the page tables.
This patch changes the string to report "level 0 translation fault",
which is far less confusing.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cpufeature.h')
0 files changed, 0 insertions, 0 deletions