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authorCatalin Marinas <catalin.marinas@arm.com>2008-11-06 16:23:08 +0300
committerCatalin Marinas <catalin.marinas@arm.com>2008-11-06 16:23:08 +0300
commit6b07d7fea0496374ff7754dc3d1dca03b2911828 (patch)
tree9a457c335982777e172fffad192c43b65d810b1e /arch/arm/mm/proc-v7.S
parent376e14218d3d791127e9b9bfbe2f99c44c2a19c2 (diff)
downloadlinux-6b07d7fea0496374ff7754dc3d1dca03b2911828.tar.xz
ARMv7: Do not set TTBR0 in __v7_setup
This register is set in __enable_mmu in the head.S file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
-rw-r--r--arch/arm/mm/proc-v7.S1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 07f82db70945..41772960fd10 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -175,7 +175,6 @@ __v7_setup:
mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
mcr p15, 0, r10, c2, c0, 2 @ TTB control register
orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
- mcr p15, 0, r4, c2, c0, 0 @ load TTB0
mcr p15, 0, r4, c2, c0, 1 @ load TTB1
mov r10, #0x1f @ domains 0, 1 = manager
mcr p15, 0, r10, c3, c0, 0 @ load domain access register