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authorThomas Gleixner <tglx@linutronix.de>2010-02-17 20:27:37 +0300
committerThomas Gleixner <tglx@linutronix.de>2010-02-17 20:28:05 +0300
commitb7e56edba4b02f2079042c326a8cd72a44635817 (patch)
treeb5042002e9747cd8fb1278d61f86d8b92a74c018 /arch/arm/mm/proc-arm920.S
parent13ca0fcaa33f6b1984c4111b6ec5df42689fea6f (diff)
parentb0483e78e5c4c9871fc5541875b3bc006846d46b (diff)
downloadlinux-b7e56edba4b02f2079042c326a8cd72a44635817.tar.xz
Merge branch 'linus' into x86/mm
x86/mm is on 32-rc4 and missing the spinlock namespace changes which are needed for further commits into this topic. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/mm/proc-arm920.S')
-rw-r--r--arch/arm/mm/proc-arm920.S11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 2b7c197cc58d..471669e2d7cb 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -207,15 +207,16 @@ ENTRY(arm920_coherent_user_range)
mov pc, lr
/*
- * flush_kern_dcache_page(void *page)
+ * flush_kern_dcache_area(void *addr, size_t size)
*
* Ensure no D cache aliasing occurs, either with itself or
* the I cache
*
- * - addr - page aligned address
+ * - addr - kernel address
+ * - size - region size
*/
-ENTRY(arm920_flush_kern_dcache_page)
- add r1, r0, #PAGE_SZ
+ENTRY(arm920_flush_kern_dcache_area)
+ add r1, r0, r1
1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
@@ -293,7 +294,7 @@ ENTRY(arm920_cache_fns)
.long arm920_flush_user_cache_range
.long arm920_coherent_kern_range
.long arm920_coherent_user_range
- .long arm920_flush_kern_dcache_page
+ .long arm920_flush_kern_dcache_area
.long arm920_dma_inv_range
.long arm920_dma_clean_range
.long arm920_dma_flush_range