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authorArnd Bergmann <arnd@arndb.de>2013-05-07 01:38:00 +0400
committerArnd Bergmann <arnd@arndb.de>2013-05-07 01:38:00 +0400
commit4183bef2e093a2f0aab45f2d5fed82b0e02aeacf (patch)
treee84c484db3746a0f3ead0fb7a2bb9e5a42b89e85 /arch/arm/mm/context.c
parent662478d060a39b8faf2b1fe2fbbb212556c2e052 (diff)
parent775c4f66fd855e68a98fc5049003810fe98e2e20 (diff)
downloadlinux-4183bef2e093a2f0aab45f2d5fed82b0e02aeacf.tar.xz
Merge branch 'late/dt' into next/dt2
This is support for the ARM Chromebook, originally scheduled as a "late" pull request. Since it's already late now, we can combine this into the existing next/dt2 branch. * late/dt: ARM: exynos: dts: cros5250: add EC device ARM: dts: Add sbs-battery for exynos5250-snow ARM: dts: Add i2c-arbitrator bus for exynos5250-snow ARM: dts: Add chip-id controller node on Exynos4/5 SoC ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree
Diffstat (limited to 'arch/arm/mm/context.c')
-rw-r--r--arch/arm/mm/context.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index a5a4b2bc42ba..2ac37372ef52 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -48,7 +48,7 @@ static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
-static DEFINE_PER_CPU(atomic64_t, active_asids);
+DEFINE_PER_CPU(atomic64_t, active_asids);
static DEFINE_PER_CPU(u64, reserved_asids);
static cpumask_t tlb_flush_pending;
@@ -215,6 +215,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) {
local_flush_bp_all();
local_flush_tlb_all();
+ dummy_flush_tlb_a15_erratum();
}
atomic64_set(&per_cpu(active_asids, cpu), asid);