summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/video
diff options
context:
space:
mode:
authorHyungwon Hwang <human.hwang@samsung.com>2015-06-12 15:59:03 +0300
committerInki Dae <inki.dae@samsung.com>2015-06-22 14:05:00 +0300
commit26269af95af83145a3bccca41344c66502fdded9 (patch)
tree10d7d375f751e2a61cc1a9c0a51c4d6c07cb7ee0 /Documentation/devicetree/bindings/video
parent77bbd8914a91fab25f567772db60e2d1372de8c6 (diff)
downloadlinux-26269af95af83145a3bccca41344c66502fdded9.tar.xz
drm/exynos: dsi: rename pll_clk to sclk_clk
This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk is actually not the pll input clock for dsi. The pll input clock comes from the board's oscillator directly. But for the backward compatibility, the old clock name "pll_clk" is also OK. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'Documentation/devicetree/bindings/video')
-rw-r--r--Documentation/devicetree/bindings/video/exynos_dsim.txt7
1 files changed, 4 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt
index 802aa7ef64e5..44659dd62b80 100644
--- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -10,13 +10,14 @@ Required properties:
- interrupts: should contain DSI interrupt
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- - clock-names: should include "bus_clk"and "pll_clk" entries
+ - clock-names: should include "bus_clk"and "sclk_mipi" entries
+ the use of "pll_clk" is deprecated
- phys: list of phy specifiers, must contain an entry for each required
entry in phy-names
- phy-names: should include "dsim" entry
- vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
- vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
- - samsung,pll-clock-frequency: specifies frequency of the "pll_clk" clock
+ - samsung,pll-clock-frequency: specifies frequency of the oscillator clock
- #address-cells, #size-cells: should be set respectively to <1> and <0>
according to DSI host bindings (see MIPI DSI bindings [1])
@@ -48,7 +49,7 @@ Example:
reg = <0x11C80000 0x10000>;
interrupts = <0 79 0>;
clocks = <&clock 286>, <&clock 143>;
- clock-names = "bus_clk", "pll_clk";
+ clock-names = "bus_clk", "sclk_mipi";
phys = <&mipi_phy 1>;
phy-names = "dsim";
vddcore-supply = <&vusb_reg>;