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| author | Diana Craciun <Diana.Craciun@freescale.com> | 2014-05-05 19:58:19 +0400 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-05-23 03:08:25 +0400 |
| commit | 385510beda1da138f2f725abd351c16e370427f1 (patch) | |
| tree | 3dcc17be9736b5478fb59106a237cd2251c72e4a /Documentation/devicetree/bindings/powerpc/fsl/cpus.txt | |
| parent | 8067bd8a12b4978e495dcbe25533ab90d24c1f83 (diff) | |
| download | linux-385510beda1da138f2f725abd351c16e370427f1.tar.xz | |
powerpc/fsl: Added binding for Freescale CoreNet coherency fabric (CCF)
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems. The CCF acts as a central interconnect for cores,
platform-level caches, memory subsystem, peripheral devices and I/O host
bridges in the system.
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
[scottwood@freescale.com: formatting and minor changes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'Documentation/devicetree/bindings/powerpc/fsl/cpus.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/cpus.txt | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt index 922c30ad90d1..f8cd2397aa04 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt @@ -20,3 +20,14 @@ PROPERTIES a property named fsl,eref-[CAT], where [CAT] is the abbreviated category name with all uppercase letters converted to lowercase, indicates that the category is supported by the implementation. + + - fsl,portid-mapping + Usage: optional + Value type: <u32> + Definition: The Coherency Subdomain ID Port Mapping Registers and + Snoop ID Port Mapping registers, which are part of the CoreNet + Coherency fabric (CCF), provide a CoreNet Coherency Subdomain + ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from + these registers should be set if the coresponding CPU should be + snooped. This property defines a bitmask which selects the bit + that should be set if this cpu should be snooped. |