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authorThomas Gleixner <tglx@linutronix.de>2020-03-15 12:53:11 +0300
committerThomas Gleixner <tglx@linutronix.de>2020-03-15 12:53:11 +0300
commit92c227554c8e735a494cd4ddca2d5bebcd705b2c (patch)
tree5def67c6c4e60387dd8cf4a04137938bb842f425 /Documentation/arm64
parent2546287c5fb363a0165933ae2181c92f03e701d0 (diff)
parentd01fd161e85904064290435f67f4ed59af5daf74 (diff)
downloadlinux-92c227554c8e735a494cd4ddca2d5bebcd705b2c.tar.xz
Merge tag 'irqchip-fixes-5.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent
Pull irqchip fixes from Marc Zyngier: - Add workaround for Cavium/Marvell ThunderX unimplemented GIC registers
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/silicon-errata.rst2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 9120e59578dc..2c08c628febd 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -110,6 +110,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
+----------------+-----------------+-----------------+-----------------------------+
+| Cavium | ThunderX GICv3 | #38539 | N/A |
++----------------+-----------------+-----------------+-----------------------------+
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
+----------------+-----------------+-----------------+-----------------------------+
| Cavium | ThunderX Core | #30115 | CAVIUM_ERRATUM_30115 |