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| author | Michael Ellerman <mpe@ellerman.id.au> | 2018-11-27 11:18:05 +0300 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2018-12-22 13:04:27 +0300 |
| commit | 423e2f94456404b49d89ef587c34022987a581e1 (patch) | |
| tree | 33e61aa792be58f70f96c700be88fb83970f5479 | |
| parent | 47918bc68b7427e961035949cc1501a864578a69 (diff) | |
| download | linux-423e2f94456404b49d89ef587c34022987a581e1.tar.xz | |
powerpc/mm: Remove very old comment in hash-4k.h
This comment talks about PTEs being 64-bits and PMD/PGD being 32-bits,
but that hasn't been true since 2005 when David Gibson implemented
4-level page tables in the commit titled "Four level pagetables for
ppc64".
Remove it.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
| -rw-r--r-- | arch/powerpc/include/asm/book3s/64/hash-4k.h | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h index 15bc16b1dc9c..cf5ba5254299 100644 --- a/arch/powerpc/include/asm/book3s/64/hash-4k.h +++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h @@ -1,11 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H #define _ASM_POWERPC_BOOK3S_64_HASH_4K_H -/* - * Entries per page directory level. The PTE level must use a 64b record - * for each page table entry. The PMD and PGD level use a 32b record for - * each entry by assuming that each entry is page aligned. - */ + #define H_PTE_INDEX_SIZE 9 #define H_PMD_INDEX_SIZE 7 #define H_PUD_INDEX_SIZE 9 |