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authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>2019-08-06 22:10:33 +0300
committerAlex Deucher <alexander.deucher@amd.com>2019-08-23 19:42:38 +0300
commit285e30049708c40a8b0221438d0300cb19a68eff (patch)
treeb101e153a53e78f935951c27971c8684d5cad485
parent5165d204acb89d540731d43fd738c3273f44cd01 (diff)
downloadlinux-285e30049708c40a8b0221438d0300cb19a68eff.tar.xz
drm/amd/display: fix dcn20 odm dpp programming
dcn20 requires special casing for odm. This change treats odm as alternative to mpc tree on dcn20. This is planned to be fixed in a future refactor Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc.c1
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c7
2 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index b0ae9d2aad0e..82c07d82e937 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2026,6 +2026,7 @@ static void commit_planes_for_stream(struct dc *dc,
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (!pipe_ctx->top_pipe &&
+ !pipe_ctx->prev_odm_pipe &&
pipe_ctx->stream &&
pipe_ctx->stream == stream) {
struct dc_stream_status *stream_status = NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index e7302587b786..0fb0a356323b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1054,8 +1054,13 @@ static void dcn20_program_all_pipe_in_tree(
if (pipe_ctx->plane_state != NULL)
dcn20_program_pipe(dc, pipe_ctx, context);
- if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
+ if (pipe_ctx->bottom_pipe != NULL) {
+ ASSERT(pipe_ctx->bottom_pipe != pipe_ctx);
dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
+ } else if (pipe_ctx->next_odm_pipe != NULL) {
+ ASSERT(pipe_ctx->next_odm_pipe != pipe_ctx);
+ dcn20_program_all_pipe_in_tree(dc, pipe_ctx->next_odm_pipe, context);
+ }
}
void dcn20_pipe_control_lock_global(