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authorDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>2018-02-27 06:27:23 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2018-02-27 23:28:10 +0300
commit06d058e1a008e202addc3bff9ab025fbcb23040f (patch)
treead776ce71e2cf784eb4ac58f38bee13d221921f5
parent3975f0aaa30371d711dc8d572f679314c415a58c (diff)
downloadlinux-06d058e1a008e202addc3bff9ab025fbcb23040f.tar.xz
drm/i915/psr: Check for power state control capability.
eDP spec says - "If PSR/PSR2 is supported, the SET_POWER_CAPABLE bit in the EDP_GENERAL_CAPABILITY_1 register (DPCD Address 00701h, bit d7) must be set to 1." Reject PSR on panels without this cap bit set as such panels cannot be controlled via SET_POWER & SET_DP_PWR_VOLTAGE register and the DP source needs to be able to do that for PSR. Thanks to Nathan for debugging this. Panel cap checks like this can be done just once, let's fix this when PSR dpcd init movement lands. Cc: Nathan D Ciobanu <nathan.d.ciobanu@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Tested-by: Nathan Ciobanu <nathan.d.ciobanu@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180227032723.15474-1-dhinakaran.pandiyan@intel.com
-rw-r--r--drivers/gpu/drm/i915/intel_psr.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b7cc6dd45c9e..1f77633fe809 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -508,6 +508,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
+ if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
+ DRM_DEBUG_KMS("PSR condition failed: panel lacks power state control\n");
+ return;
+ }
+
/*
* FIXME psr2_support is messed up. It's both computed
* dynamically during PSR enable, and extracted from sink