diff options
| author | Joel Stanley <joel@jms.id.au> | 2020-08-12 14:13:29 +0300 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2020-08-13 01:55:13 +0300 |
| commit | 092c0e20139efe8b4fb630281bd9c99c74ec4a54 (patch) | |
| tree | d01c09fda5aa6764625ea2688355baa8cc3c4240 | |
| parent | ee41b2b489259f01585e49327377f62b76a24748 (diff) | |
| download | linux-092c0e20139efe8b4fb630281bd9c99c74ec4a54.tar.xz | |
ARM: aspeed: g5: Do not set sirq polarity
A feature was added to the aspeed vuart driver to configure the vuart
interrupt (sirq) polarity according to the LPC/eSPI strapping register.
Systems that depend on a active low behaviour (sirq_polarity set to 0)
such as OpenPower boxes also use LPC, so this relationship does not
hold.
The property was added for a Tyan S7106 system which is unfortuantly not
supported in the kernel tree. Should other systems wish to use this
feature of the driver they should add it to the machine device tree.
OpenBMC-Staging-Count: 1
Fixes: c791fc76bc72 ("arm: dts: aspeed: Add vuart aspeed,sirq-polarity-sense...")
Cc: stable@vger.kernel.org
Alexander A. Filippov <a.filippov@yadro.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
| -rw-r--r-- | arch/arm/boot/dts/aspeed-g5.dtsi | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 51affa6a63e5..19288495f41a 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -429,7 +429,6 @@ interrupts = <8>; clocks = <&syscon ASPEED_CLK_APB>; no-loopback-test; - aspeed,sirq-polarity-sense = <&syscon 0x70 25>; status = "disabled"; }; |