Intel OpenBMC Linux kernel source tree (mirror) https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.14-intel 2021-06-18T13:29:32+00:00 2021-06-18T13:29:32+00:00 Srinivas Pandruvada srinivas.pandruvada@linux.intel.com 2021-06-10T21:36:35+00:00 urn:sha1:307722e872658ee8cfa4ee0f9a7aa9a1b2207417 This release adds following change: - Fix reporting of memory frequency Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> 2021-06-18T13:29:23+00:00 Srinivas Pandruvada srinivas.pandruvada@linux.intel.com 2021-05-12T10:17:32+00:00 urn:sha1:159f130f60f402273b235801d1fde3fc115c6795 The uncore memory frequency value from the mailbox command CONFIG_TDP_GET_MEM_FREQ needs to be scaled based on the platform for display. There is no single constant multiplier. This change introduces CPU model specific memory frequency multiplier. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> 2021-05-05T19:24:29+00:00 Linus Torvalds torvalds@linux-foundation.org 2021-05-05T19:24:29+00:00 urn:sha1:d8cb379cda885ac172454d7e680da65ebd6676b1 Pull turbostat updates from Len Brown: "Bug fixes and a smattering of features" * 'turbostat' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux: (21 commits) tools/power turbostat: version 2021.05.04 tools/power turbostat: Support "turbostat --hide idle" tools/power turbostat: elevate priority of interval mode tools/power turbostat: formatting tools/power turbostat: rename tcc variables tools/power turbostat: add TCC Offset support tools/power turbostat: save original CPU model tools/power turbostat: Fix Core C6 residency on Atom CPUs tools/power turbostat: Print the C-state Pre-wake settings tools/power turbostat: Enable tsc_tweak for Elkhart Lake and Jasper Lake tools/power turbostat: unmark non-kernel-doc comment tools/power/turbostat: Remove Package C6 Retention on Ice Lake Server tools/power turbostat: Fix offset overflow issue in index converting tools/power/turbostat: Fix turbostat for AMD Zen CPUs tools/power turbostat: update version number tools/power turbostat: Fix DRAM Energy Unit on SKX Revert "tools/power turbostat: adjust for temperature offset" tools/power turbostat: Support Ice Lake D tools/power turbostat: Support Alder Lake Mobile tools/power turbostat: print microcode patch level ... 2021-05-05T00:01:09+00:00 Len Brown len.brown@intel.com 2021-05-04T23:58:08+00:00 urn:sha1:3c070b2abf85b92455c2721d0a9edc68893ab6c1 Signed-off-by: Len Brown <len.brown@intel.com> 2021-05-05T00:01:09+00:00 Len Brown len.brown@intel.com 2021-05-04T23:56:17+00:00 urn:sha1:b60c573dc241ab3a8719e990d86a0011b79eebcb As idle, in particular, can have many columns on some machines... Make it easy to ignore them all at once. Signed-off-by: Len Brown <len.brown@intel.com> 2021-05-05T00:01:09+00:00 Len Brown len.brown@intel.com 2021-05-04T23:27:34+00:00 urn:sha1:38c6663a68903cf1187003129cd1873551979865 This makes interval mode less likely to see delayed results on a heavily loaded system. Signed-off-by: Len Brown <len.brown@intel.com> 2021-05-05T00:01:09+00:00 Len Brown len.brown@intel.com 2021-05-04T23:21:34+00:00 urn:sha1:1b439f01b67c77a374adbbd97ad0c745b7abb09b Spring is here... run a long overdue Lendent on turbostat.c no functional change Signed-off-by: Len Brown <len.brown@intel.com> 2021-05-05T00:01:09+00:00 Zhang Rui rui.zhang@intel.com 2021-04-26T10:49:26+00:00 urn:sha1:55279aef754c5eab170077ae4ba4ebd304dea64f There are two TCC activation temeprature. One is the default TCC activation temperature, also known as TJ_MAX. Another one is the effective TCC activation temperature, which is the subtraction of default TCC activation temperature and TCC offset. The name of variable tcc_activation_temp might be misleading here. Thus rename tcc_activation_temp to tj_max, and use tcc_default and tcc_offset to calculate the effective TCC activation temperature. No functional change in this patch. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> 2021-05-05T00:01:08+00:00 Zhang Rui rui.zhang@intel.com 2021-04-21T15:22:14+00:00 urn:sha1:0b9a0b9be991656f125b58a240065cdf72077244 The length of TCC Offset bits varies on different platforms. Decode TCC Offset bits only for the platforms that we have verified. For the others, only show default TCC activation temperature. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> 2021-05-05T00:01:08+00:00 Zhang Rui rui.zhang@intel.com 2021-04-26T02:05:27+00:00 urn:sha1:e9d3092f6d7c21031c8ac10ba2016ae0482a39fe CPU model may get changed in intel_model_duplicates() for code reuse. But there are still some cases we need the original CPU model to handle minor differences between generations. Thus save the original CPU model. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>