Intel OpenBMC Linux kernel source tree (mirror) https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=v4.4 2016-01-05T23:07:33+00:00 2016-01-05T23:07:33+00:00 Mark Brown broonie@kernel.org 2016-01-05T23:07:33+00:00 urn:sha1:84a5347b89690aae2c9d08f64219d71108c70011 2016-01-05T23:07:32+00:00 Mark Brown broonie@kernel.org 2016-01-05T23:07:32+00:00 urn:sha1:7a78d9439ae9515a8ed2b97c267e54da92f2def0 2015-12-30T16:35:07+00:00 Bard Liao bardliao@realtek.com 2015-12-30T07:33:21+00:00 urn:sha1:ca8457bb02d8ecddf7f49ab874127dd4df782b16 Add system clock detection to prevent output DC from SPO. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org> 2015-12-24T19:12:48+00:00 Nikesh Oswal Nikesh.Oswal@cirrus.com 2015-12-23T14:18:05+00:00 urn:sha1:e73694d871867cae8471d2350ce89acb38bc2b63 For a sample rate of 12kHz the bclk was taken from the 44.1kHz table as we test for a multiple of 8kHz. This patch fixes this issue by testing for multiples of 4kHz instead. Signed-off-by: Nikesh Oswal <Nikesh.Oswal@cirrus.com> Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org 2015-12-23T00:23:27+00:00 Mark Brown broonie@kernel.org 2015-12-23T00:23:27+00:00 urn:sha1:3dd5fc0eeb5d7cc07b8e3e383037261799b38897 2015-12-17T12:13:40+00:00 Jean-Michel Hautbois jhautbois@gmail.com 2015-12-17T10:07:23+00:00 urn:sha1:c803cc2dcd722e08020c1ba63bb5ceece4a19fdb When power up, a "pop" is heard on line-in and mic-in. An analysis of the PCM shows it lasts ~400ms and looks like a filter response. VAG power up should be delayed by 400ms as VAG power down is. Signed-off-by: Jean-Michel Hautbois <jean-michel.hautbois@veo-labs.com> Signed-off-by: Mark Brown <broonie@kernel.org> 2015-12-12T22:22:06+00:00 Mans Rullgard mans@mansr.com 2015-12-11T11:27:08+00:00 urn:sha1:1ea5998afe903384ddc16391d4c023cd4c867bea Attempting to use this codec driver triggers a BUG() in regcache_sync() since no cache type is set. The register map of this device is fairly small and has few holes so a flat cache is suitable. Signed-off-by: Mans Rullgard <mans@mansr.com> Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org 2015-12-12T22:06:20+00:00 John Keeping john@metanate.com 2015-11-20T11:42:22+00:00 urn:sha1:352d52e2442f42539c76d8a13d795ccab7079b26 These are all off by one; the playback and bypass switches are the top two bits of the registers, which are at shifts 7 and 6 not 8 and 7. Signed-off-by: John Keeping <john@metanate.com> Signed-off-by: Mark Brown <broonie@kernel.org> 2015-12-09T20:42:19+00:00 John Keeping john@metanate.com 2015-12-09T11:38:13+00:00 urn:sha1:84ebac4d04d25ac5c1b1dc3ae621fd465eb38f4e This is using completely the wrong mask and value when updating the register. Since the correct values are already defined in the header, switch to using a table with explicit constants rather than shifting the array index. Signed-off-by: John Keeping <john@metanate.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org 2015-11-25T17:57:54+00:00 Mark Brown broonie@kernel.org 2015-11-25T17:57:54+00:00 urn:sha1:923f1cbf2e45f6292a01de959031a8efeabede78