<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/include/linux/mlx5/mlx5_ifc.h, branch master</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=master</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2017-07-27T13:40:17+00:00</updated>
<entry>
<title>net/mlx5e: Add field select to MTPPS register</title>
<updated>2017-07-27T13:40:17+00:00</updated>
<author>
<name>Eugenia Emantayev</name>
<email>eugenia@mellanox.com</email>
</author>
<published>2017-05-25T13:09:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=fa3676885e3b5be1edfa1b2cc775e20a45b34a19'/>
<id>urn:sha1:fa3676885e3b5be1edfa1b2cc775e20a45b34a19</id>
<content type='text'>
In order to mark relevant fields while setting the MTPPS register
add field select. Otherwise it can cause a misconfiguration in
firmware.

Fixes: ee7f12205abc ('net/mlx5e: Implement 1PPS support')
Signed-off-by: Eugenia Emantayev &lt;eugenia@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Fix mlx5_ifc_mtpps_reg_bits structure size</title>
<updated>2017-07-27T13:40:17+00:00</updated>
<author>
<name>Eugenia Emantayev</name>
<email>eugenia@mellanox.com</email>
</author>
<published>2017-05-25T12:11:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=0b794ffae7afa7c4e5accac8791c4b78e8d080ce'/>
<id>urn:sha1:0b794ffae7afa7c4e5accac8791c4b78e8d080ce</id>
<content type='text'>
Fix miscalculation in reserved_at_1a0 field.

Fixes: ee7f12205abc ('net/mlx5e: Implement 1PPS support')
Signed-off-by: Eugenia Emantayev &lt;eugenia@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: IPSec, Innova IPSec offload infrastructure</title>
<updated>2017-06-27T13:36:47+00:00</updated>
<author>
<name>Ilan Tayari</name>
<email>ilant@mellanox.com</email>
</author>
<published>2017-04-18T13:04:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=547eede070eb981f1442e494f08f4567dcf1d1c7'/>
<id>urn:sha1:547eede070eb981f1442e494f08f4567dcf1d1c7</id>
<content type='text'>
Add Innova IPSec ESP crypto offload configuration paths.
Detect Innova IPSec device and set the NETIF_F_HW_ESP flag.
Configure Security Associations using the API introduced in a previous
patch.

Add Software-parser hardware descriptor layout
Software-Parser (swp) is a hardware feature in ConnectX which allows the
host software to specify protocol header offsets in the TX path, thus
overriding the hardware parser.
This is useful for protocols that the ASIC may not be able to parse on
its own.

Note that due to inline metadata, XDP is not supported in Innova IPSec.

Signed-off-by: Ilan Tayari &lt;ilant@mellanox.com&gt;
Signed-off-by: Yossi Kuperman &lt;yossiku@mellanox.com&gt;
Signed-off-by: Yevgeny Kliteynik &lt;kliteyn@mellanox.com&gt;
Signed-off-by: Boris Pismenny &lt;borisp@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: FPGA, Add SBU infrastructure</title>
<updated>2017-06-27T13:36:47+00:00</updated>
<author>
<name>Ilan Tayari</name>
<email>ilant@mellanox.com</email>
</author>
<published>2017-04-18T10:10:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=a9956d35d199beb406727a4496bc5d7f09c82976'/>
<id>urn:sha1:a9956d35d199beb406727a4496bc5d7f09c82976</id>
<content type='text'>
Add interface to initialize and interact with Innova FPGA SBU
connections.
A client driver may use these functions to set up a high-speed DMA
connection with its SBU hardware logic, and send/receive messages
over this connection.

A later patch in this patchset will make use of these functions for
Innova IPSec offload in mlx5 Ethernet driver.

Add commands to retrieve Innova FPGA SBU capabilities, and to
read/write Innova FPGA configuration space registers and memory,
over internal I2C.

At high level, the FPGA configuration space is divided such:
 0x00000000 - 0x007fffff is reserved for the SBU
 0x00800000 - 0xffffffff is reserved for the Shell
0x400000000 - ...        is DDR memory

A later patchset will add support for accessing FPGA CrSpace and memory
over a high-speed connection. This is the reason for the ACCESS_TYPE
enumeration, which currently only supports I2C.

Signed-off-by: Ilan Tayari &lt;ilant@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: FPGA, Add FW commands for FPGA QPs</title>
<updated>2017-06-27T13:36:47+00:00</updated>
<author>
<name>Ilan Tayari</name>
<email>ilant@mellanox.com</email>
</author>
<published>2017-03-27T11:52:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=6062118d5cd2b90369278cdf831aeffb84ae3943'/>
<id>urn:sha1:6062118d5cd2b90369278cdf831aeffb84ae3943</id>
<content type='text'>
The FPGA QP is a high-bandwidth communication channel between the host
CPU and the FPGA device. It allows performing DMA operations between
host memory and the FPGA logic via the ConnectX chip.

Add ConnectX FW commands which create and manipulate FPGA QPs.

Signed-off-by: Ilan Tayari &lt;ilant@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Fix offset of hca cap reserved field</title>
<updated>2017-06-22T11:30:14+00:00</updated>
<author>
<name>Or Gerlitz</name>
<email>ogerlitz@mellanox.com</email>
</author>
<published>2017-06-13T15:12:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=137ffd15f71ec29ff1a57728081569698591225a'/>
<id>urn:sha1:137ffd15f71ec29ff1a57728081569698591225a</id>
<content type='text'>
The offending commit pushed fwd the field by two bits but
didn't increment the offset, fix that. Currently, no damage
was done b/c this is just a field name, but lets have it right.

Fixes: f32f5bd2eb7e ('net/mlx5: Configure cache line size for start and end padding')
Signed-off-by: Or Gerlitz &lt;ogerlitz@mellanox.com&gt;
Reported-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Enhance MCAM reg to allow query on access reg support</title>
<updated>2017-06-22T11:30:13+00:00</updated>
<author>
<name>Or Gerlitz</name>
<email>ogerlitz@mellanox.com</email>
</author>
<published>2017-06-11T12:25:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=0ab87743cc8c5bcd482daf71961ed5fc45349e01'/>
<id>urn:sha1:0ab87743cc8c5bcd482daf71961ed5fc45349e01</id>
<content type='text'>
Enhance MCAM to allow the driver to query which access regs are
supported. For now, expose the regs needed for FW flashing.

Signed-off-by: Or Gerlitz &lt;ogerlitz@mellanox.com&gt;
Reviewed-by: Gal Pressman &lt;galp@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Add MCC (Management Component Control) register definitions</title>
<updated>2017-06-22T11:30:13+00:00</updated>
<author>
<name>Or Gerlitz</name>
<email>ogerlitz@mellanox.com</email>
</author>
<published>2017-04-18T10:35:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=4717628938423fcba0aa8fa889e9fed4eb6a655f'/>
<id>urn:sha1:4717628938423fcba0aa8fa889e9fed4eb6a655f</id>
<content type='text'>
MCC (Management Component Control) allows to control a firmware
component update.

MCDA (Management Component Data Access) allows to read and write
a firmware component.

MCQI (Management Component Query Information) allows to query
information about firmware components.

Signed-off-by: Or Gerlitz &lt;ogerlitz@mellanox.com&gt;
Signed-off-by: Yotam Gigi &lt;yotamg@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: Add header re-write offloading of IPv6 hop-limit</title>
<updated>2017-06-22T11:30:13+00:00</updated>
<author>
<name>Or Gerlitz</name>
<email>ogerlitz@mellanox.com</email>
</author>
<published>2017-06-13T08:09:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=0c0316f516f51e6fcd0b23d61c37f9f5f846f978'/>
<id>urn:sha1:0c0316f516f51e6fcd0b23d61c37f9f5f846f978</id>
<content type='text'>
For environments where flow-based ipv6 router is offloaded.

Signed-off-by: Or Gerlitz &lt;ogerlitz@mellanox.com&gt;
Reviewed-by: Paul Blakey &lt;paulb@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: Offload TC matching on ip ttl</title>
<updated>2017-06-22T11:30:13+00:00</updated>
<author>
<name>Or Gerlitz</name>
<email>ogerlitz@mellanox.com</email>
</author>
<published>2017-06-07T14:49:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=a8ade55ffd1c1acef053a2d05f30e91a1c114f58'/>
<id>urn:sha1:a8ade55ffd1c1acef053a2d05f30e91a1c114f58</id>
<content type='text'>
Enable offloading of TC matching on ip ttl / hop-limit

As matching on ttl is supported only by newer HW brands (ConnectX-5),
we should do capability check before attempting to offload that.

Signed-off-by: Or Gerlitz &lt;ogerlitz@mellanox.com&gt;
Reviewed-by: Paul Blakey &lt;paulb@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
</feed>
