BMC/Intel-BMC/linux.git/include/linux/irqchip/arm-gic.h, branch dev

irqchip: gic: Drop support for gic_arch_extn

2015-04-24T18:57:06+00:00

Now that the users of gic_arch_extn have been fixed, drop the "feature" for good. This leads to the removal of some now useless locking. Signed-off-by: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org Cc: Jason Cooper Signed-off-by: Thomas Gleixner

Merge branch 'irqchip/stacked-irq_set_wake' into irqchip/core

2015-04-10T22:58:19+00:00

Conflicts: drivers/irqchip/irq-gic.c

irqchip: gic: Add an entry point to set up irqchip flags

2015-03-15T01:27:42+00:00

A common use of gic_arch_extn is to set up additional flags to the GIC irqchip. It looks like a benign enough hack that doesn't really require the users of that feature to be converted to stacked domains. Add a gic_set_irqchip_flags() function that platform code can call instead of using the dreaded gic_arch_extn. Signed-off-by: Marc Zyngier Link: https://lkml.kernel.org/r/1426088737-15817-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper

irqchip: gic: Get rid of routable domain

2015-03-15T00:55:58+00:00

The only user of the so called "routable domain" functionality now being fixed, let's clean up the GIC. Acked-by: Tony Lindgren Signed-off-by: Marc Zyngier Link: https://lkml.kernel.org/r/1426088629-15377-5-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper

irqchip: gic: Remove warning by including linux/irqdomain.h

2014-11-28T16:42:13+00:00

Commit 853a33ce6932 irqchip: gic-v2m: Add support for ARM GICv2m MSI(-X) doorbell Introduced a series of warnings when building ARM multi_v7_defconfig: include/linux/irqchip/arm-gic.h:109:53: warning: its scope is only this definition or declaration, which is probably not what you want In file included from arch/arm/mach-ux500/pm.c:13:0: include/linux/irqchip/arm-gic.h:109:53: warning: 'struct irq_domain' declared inside parameter list int gicv2m_of_init(struct device_node *node, struct irq_domain *parent); ^ Fix this by adding the proper include. Signed-off-by: Jason Cooper [ jac merged much more correct version from Marc into this patch ] Signed-off-by: Marc Zyngier Acked-by: Will Deacon Link: https://lkml.kernel.org/r/1417170975-1163-1-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper

irqchip: gic-v2m: Add support for ARM GICv2m MSI(-X) doorbell

2014-11-26T15:55:18+00:00

ARM GICv2m specification extends GICv2 to support MSI(-X) with a new register frame. This allows a GICv2 based system to support MSI with minimal changes. Signed-off-by: Suravee Suthikulpanit [maz: converted the driver to use stacked irq domains, updated changelog] Signed-off-by: Marc Zyngier Link: https://lkml.kernel.org/r/1416941243-7181-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper

irqchip: gic: Preserve gic V2 bypass bits in cpu ctrl register

2014-08-19T15:08:07+00:00

This change is made to preserve the GIC v2 bypass bits in the GIC_CPU_CTRL register (also known as the GICC_CTLR register in spec). This code will preserve all bits configured by the bootloader regarding v2 bypass group bits. In the X-Gene platform, the bypass functionality is not used and bypass bits should not be changed by the kernel gic code as it could lead to incorrect behavior. Signed-off-by: Feng Kan Reviewed-by: Vinayak Kale Reviewed-by: Anup Patel Link: https://lkml.kernel.org/r/1406757419-18729-3-git-send-email-fkan@apm.com Signed-off-by: Jason Cooper

irqchip: gic: Replace hex numbers with defines.

2014-08-19T15:07:46+00:00

This is to cleanup some hex numbers used in the code and replace them with defines to make the code cleaner. Signed-off-by: Feng Kan Reviewed-by: Anup Patel Link: https://lkml.kernel.org/r/1406757419-18729-2-git-send-email-fkan@apm.com Signed-off-by: Jason Cooper

irqchip: gic: Use mask field in GICC_IAR

2014-05-19T00:35:23+00:00

Bit[9:0] is interrupt ID field in GICC_IAR. Bit[12:10] is CPU ID field, and others are reserved. So we should use GICC_IAR_INT_ID_MASK to get interrupt ID. It's not a good way to use ~0x1c00 (CPU ID field) to get interrupt ID. Signed-off-by: Haojian Zhuang Link: https://lkml.kernel.org/r/1399795571-17231-3-git-send-email-haojian.zhuang@linaro.org Signed-off-by: Jason Cooper

DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

2014-02-05T14:38:00+00:00

In some socs the gic can be preceded by a crossbar IP which routes the peripheral interrupts to the gic inputs. The peripheral interrupts are associated with a fixed crossbar input line and the crossbar routes that to one of the free gic input line. The DT entries for peripherals provides the fixed crossbar input line as its interrupt number and the mapping code should associate this with a free gic input line. This patch adds the support inside the gic irqchip to handle such routable irqs. The routable irqs are registered in a linear domain. The registered routable domain's callback should be implemented to get a free irq and to configure the IP to route it. Cc: Thomas Gleixner Cc: Linus Walleij Cc: Santosh Shilimkar Cc: Russell King Cc: Tony Lindgren Cc: Rajendra Nayak Cc: Marc Zyngier Cc: Grant Likely Cc: Rob Herring Signed-off-by: Sricharan R Reviewed-by: Thomas Gleixner Acked-by: Santosh Shilimkar Acked-by: Linus Walleij