BMC/Intel-BMC/linux.git/include/linux/clk/at91_pmc.h, branch dev-5.1

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-07-02T05:03:44+00:00

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman (cherry picked from commit 2874c5fd284268364ece81a7bd936f3c8168e567) Signed-off-by: Joel Stanley

ARM: at91: pm: add PMC fast startup registers defines

2018-07-17T13:08:07+00:00

Add PMC fast startup registers defines. Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni

ARM: at91: pm: Add ULP1 mode support

2018-07-17T13:08:02+00:00

In the ULP1 mode, in order to achieve the lowest power consumption with the system in retention mode and be able to resume on the wake up events, all the clocks are shut off, inclusive the embedded 12MHz RC oscillator, and the number of wake up sources is limited as well. When the wake up event is asserted, the embedded 12MHz RC oscillator restarts automatically. The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2. The previous size of pm_suspend.o was 2148 bytes. With the addition of ULP1 mode the new size of pm_suspend.o raised at 2456 bytes. Signed-off-by: Wenyou Yang Signed-off-by: Ludovic Desroches [claudiu.beznea@microchip.com: aligned with 4.18-rc1] Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni

clk: at91: add audio pll clock drivers

2017-09-01T22:46:52+00:00

This new clock driver set allows to have a fractional divided clock that would generate a precise clock particularly suitable for audio applications. The main audio pll clock has two children clocks: one that is connected to the PMC, the other that can directly drive a pad. As these two routes have different enable bits and different dividers and divider formulas, they are handled by two different drivers. Each of them could modify the rate of the main audio pll parent. The main audio pll clock can output 620MHz to 700MHz. Signed-off-by: Nicolas Ferre Signed-off-by: Quentin Schulz Acked-by: Boris Brezillon Signed-off-by: Stephen Boyd

clk: at91: pmc: drop at91_pmc_base

2016-02-17T16:53:03+00:00

at91_pmc_base is not used anymore, remove it along with at91_pmc_read and at91_pmc_write. Signed-off-by: Alexandre Belloni Acked-by: Boris Brezillon Acked-by: Stephen Boyd

clk: at91: add generated clock driver

2015-10-01T19:48:11+00:00

Add a new type of clocks that can be provided to a peripheral. In addition to the peripheral clock, this new clock that can use several input clocks as parents can generate divided rates. This would allow a peripheral to have finer grained clocks for generating a baud rate, clocking an asynchronous part or having more options in frequency. Signed-off-by: Nicolas Ferre Signed-off-by: Boris Brezillon [sboyd@codeaurora.org: Transition to new clk_hw provider APIs] Signed-off-by: Stephen Boyd

clk: at91: add PMC sama5d2 support

2015-10-01T19:39:44+00:00

Add support for the new sama5d2 SoC and adapt capabilities. Signed-off-by: Nicolas Ferre Signed-off-by: Boris Brezillon Signed-off-by: Stephen Boyd

clk: at91: cleanup PMC header file for PCR register fields

2015-10-01T19:39:41+00:00

Add _MASK and _OFFSET values and cleanup register fields layout. Signed-off-by: Nicolas Ferre Signed-off-by: Boris Brezillon Signed-off-by: Stephen Boyd

clk: at91: change to using endian agnositc IO

2015-04-11T21:38:39+00:00

Change to using endian agnostic _relaxed IO accessors instead of __raw Signed-off-by: Ben Dooks -- CC: Andrew Victor CC: Nicolas Ferre CC: Jean-Christophe Plagniol-Villard CC: Mike Turquette (maintainer:COMMON CLK FRAMEWORK) CC: Stephen Boyd (maintainer:COMMON CLK FRAMEWORK) CC: linux-kernel@vger.kernel.org (open list:COMMON CLK FRAMEWORK) Signed-off-by: Michael Turquette

clk: at91: add a driver for the h32mx clock

2014-09-22T09:38:59+00:00

Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix interconnect (h32mx) has a clock that can be setup at the half of the h64mx clock (which is mck). The h32mx clock can not exceed 90 MHz. Signed-off-by: Alexandre Belloni Acked-by: Boris Brezillon Signed-off-by: Nicolas Ferre