<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/include/dt-bindings, branch dev-5.15-intel</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.15-intel</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.15-intel'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2021-11-05T07:22:13+00:00</updated>
<entry>
<title>Fix reset index of LPC and eSPI</title>
<updated>2021-11-05T07:22:13+00:00</updated>
<author>
<name>Jae Hyun Yoo</name>
<email>jae.hyun.yoo@intel.com</email>
</author>
<published>2021-01-12T16:57:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=690a686539fab8d093292b403be9b28b9c62edb8'/>
<id>urn:sha1:690a686539fab8d093292b403be9b28b9c62edb8</id>
<content type='text'>
AST2600 A1 has separate reset control for LPC and eSPI so this
commit fix the index definition to make it work on AST2600 A1.

Signed-off-by: Jae Hyun Yoo &lt;jae.hyun.yoo@intel.com&gt;
</content>
</entry>
<entry>
<title>enable AST2600 I3C</title>
<updated>2021-11-05T07:22:10+00:00</updated>
<author>
<name>Jae Hyun Yoo</name>
<email>jae.hyun.yoo@intel.com</email>
</author>
<published>2020-05-07T01:11:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=7b3be052d04ef830ab49db2c2b5bfb7ac42a7498'/>
<id>urn:sha1:7b3be052d04ef830ab49db2c2b5bfb7ac42a7498</id>
<content type='text'>
This commit ports I3C related changes from Aspeed SDK v00.05.05.
It also includes Vitor's I3C cdev implementation which isn't
upstreamed yet so it should be refined later.

Signed-off-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
Signed-off-by: Vitor Soares &lt;soares@synopsys.com&gt;
Signed-off-by: Jae Hyun Yoo &lt;jae.hyun.yoo@intel.com&gt;
</content>
</entry>
<entry>
<title>ast2600: enable high speed uart in kernel.</title>
<updated>2021-11-05T07:22:09+00:00</updated>
<author>
<name>Kuiying Wang</name>
<email>kuiying.wang@intel.com</email>
</author>
<published>2019-12-13T08:15:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=057cdbfd1cf64959f6d4b7233005b6a35e2efc55'/>
<id>urn:sha1:057cdbfd1cf64959f6d4b7233005b6a35e2efc55</id>
<content type='text'>
Tested:
1. Config baud rate to 921600 in BIOS setup page
2. BMC could change env variable "hostserialcfg" to 1.
3. BMC is force to reboot and SPA baud rate is changed to 921600 successfully.
4. It is same for back to 115200.

Signed-off-by: Kuiying Wang &lt;kuiying.wang@intel.com&gt;
</content>
</entry>
<entry>
<title>Add high speed baud rate support for UART</title>
<updated>2021-11-05T07:22:06+00:00</updated>
<author>
<name>Yong Li</name>
<email>yong.b.li@linux.intel.com</email>
</author>
<published>2019-01-02T07:06:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=51181b65c8d67612ac13e291173f118707f55c62'/>
<id>urn:sha1:51181b65c8d67612ac13e291173f118707f55c62</id>
<content type='text'>
In order to support high speed baud rate(921600 bps),
the default UART clock(24MHz) needs to be switched
to 192MHz(from USB2.0 port1 PHY).

Create a new 192M Hz clock and assign it to uart,
based on uart clock source configuration in SCU4C.

bootloader(u-boot) will set SCU4C based on the environment configuration

Signed-off-by: Yong Li &lt;yong.b.li@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>arm: dts: base aspeed g6 dtsi fixups</title>
<updated>2021-11-05T07:22:05+00:00</updated>
<author>
<name>Vernon Mauery</name>
<email>vernon.mauery@linux.intel.com</email>
</author>
<published>2019-09-12T07:55:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=bda134ac56c65e4f45a1c930dfab43e1e5987987'/>
<id>urn:sha1:bda134ac56c65e4f45a1c930dfab43e1e5987987</id>
<content type='text'>
Additions to the base g6 dtsi file for Aspeed ast2600 systems.
This mostly includes entries for the drivers that are not upstream.

Signed-off-by: Vernon Mauery &lt;vernon.mauery@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'linux-watchdog-5.15-rc1' of git://www.linux-watchdog.org/linux-watchdog</title>
<updated>2021-09-07T20:52:46+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-09-07T20:52:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=4c00e1e2e58eefb288ba9ef585b6f19e1f33bf1e'/>
<id>urn:sha1:4c00e1e2e58eefb288ba9ef585b6f19e1f33bf1e</id>
<content type='text'>
Pull watchdog updates from Wim Van Sebroeck:

 - add Mediatek MT7986 &amp; MT8195 wdt support

 - add Maxim MAX63xx

 - drop bd70528 support

 - rewrite ixp4xx to watchdog framework

 - constify static struct watchdog_ops for sl28cpld_wdt, mpc8xxx_wdt and
   tqmx86

 - introduce watchdog_dev_suspend/resume

 - several fixes and improvements

* tag 'linux-watchdog-5.15-rc1' of git://www.linux-watchdog.org/linux-watchdog:
  dt-bindings: watchdog: Add compatible for Mediatek MT7986
  watchdog: ixp4xx: Rewrite driver to use core
  watchdog: Start watchdog in watchdog_set_last_hw_keepalive only if appropriate
  watchdog: max63xx_wdt: Add device tree probing
  dt-bindings: watchdog: Add Maxim MAX63xx bindings
  watchdog: mediatek: mt8195: add wdt support
  dt-bindings: reset: mt8195: add toprgu reset-controller header file
  watchdog: tqmx86: Constify static struct watchdog_ops
  watchdog: mpc8xxx_wdt: Constify static struct watchdog_ops
  watchdog: sl28cpld_wdt: Constify static struct watchdog_ops
  watchdog: iTCO_wdt: Fix detection of SMI-off case
  watchdog: bcm2835_wdt: consider system-power-controller property
  watchdog: imx2_wdg: notify wdog core to stop ping worker on suspend
  watchdog: introduce watchdog_dev_suspend/resume
  watchdog: Fix NULL pointer dereference when releasing cdev
  watchdog: only run driver set_pretimeout op if device supports it
  watchdog: bd70528 drop bd70528 support
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2021-09-02T21:22:56+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-09-02T21:22:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=c793011242d182e5f12800c12dbaf37af80be735'/>
<id>urn:sha1:c793011242d182e5f12800c12dbaf37af80be735</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.15 kernel cycle, no
  core changes at all this time, just driver work!

  New drivers:

   - New subdriver for Intel Keem Bay (an ARM-based SoC)

   - New subdriver for Qualcomm MDM9607 and SM6115

   - New subdriver for ST Microelectronics STM32MP135

   - New subdriver for Freescale i.MX8ULP ("Ultra Low Power")

   - New subdriver for Ingenic X2100

   - Support for Qualcomm PMC8180, PMC8180C, SA8155p-adp PMIC GPIO

   - Support Samsung Exynos850

   - Support Renesas RZ/G2L

  Enhancements:

   - A major refactoring of the Rockchip driver, breaking part of it out
     to a separate GPIO driver in drivers/gpio

   - Pin bias support on Renesas r8a77995

   - Add SCI pins support to Ingenic JZ4755 and JZ4760

   - Mediatek device tree bindings converted to YAML"

* tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (53 commits)
  pinctrl: renesas: Add RZ/G2L pin and gpio controller driver
  pinctrl: samsung: Add Exynos850 SoC specific data
  dt-bindings: pinctrl: samsung: Add Exynos850 doc
  MAINTAINERS: Add maintainers for amd-pinctrl driver
  pinctrl: Add Intel Keem Bay pinctrl driver
  dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver
  pinctrl: zynqmp: Drop pinctrl_unregister for devm_ registered device
  dt-bindings: pinctrl: qcom-pmic-gpio: Remove the interrupts property
  dt-bindings: pinctrl: qcom-pmic-gpio: Convert qcom pmic gpio bindings to YAML
  dt-bindings: pinctrl: mt8195: Use real world values for drive-strength arguments
  dt-bindings: mediatek: convert pinctrl to yaml
  arm: dts: mt8183: Move pinfunc to include/dt-bindings/pinctrl
  arm: dts: mt8135: Move pinfunc to include/dt-bindings/pinctrl
  pinctrl: ingenic: Add .max_register in regmap_config
  pinctrl: ingenic: Fix bias config for X2000(E)
  pinctrl: ingenic: Fix incorrect pull up/down info
  pinctrl: Ingenic: Add pinctrl driver for X2100.
  dt-bindings: pinctrl: Add bindings for Ingenic X2100.
  pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760.
  pinctrl: Ingenic: Improve the code.
  ...
</content>
</entry>
<entry>
<title>Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux</title>
<updated>2021-09-02T21:17:24+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-09-02T21:17:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=75d6e7d9ced83e937757e278c3ce1ccd6606a96a'/>
<id>urn:sha1:75d6e7d9ced83e937757e278c3ce1ccd6606a96a</id>
<content type='text'>
Pull clk updates from Stephen Boyd:
 "Nothing changed in the clk framework core this time around. We did get
  some updates to the basic clk types to use determine_rate for the
  divider type and add a power of two fractional divider flag though.

  Otherwise, this is a collection of clk driver updates. More than half
  the diffstat is in the Qualcomm clk driver where we add a bunch of
  data to describe clks on various SoCs and fix bugs. The other big new
  thing in here is the Mediatek MT8192 clk driver. That's been under
  review for a while and it's nice to see that it's finally upstream.

  Beyond that it's the usual set of minor fixes and tweaks to clk
  drivers. There are some non-clk driver bits in here which have all
  been acked by the respective maintainers.

  New Drivers:
   - Support video, gpu, display clks on qcom sc7280 SoCs
   - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs
   - Multimedia clks (MMCC) on qcom MSM8994/MSM8992
   - RPMh clks on qcom SM6350 SoCs
   - Support for Mediatek MT8192 SoCs
   - Add display (DU and DSI) clocks on Renesas R-Car V3U
   - Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and
     resets on Renesas RZ/G2L

  Updates:
   - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators
   - Add power of two flag to fractional divider clk type
   - Migrate some clk drivers to clk_divider_ops.determine_rate
   - Migrate to clk_parent_data in gcc-sdm660
   - Fix CLKOUT clocks on i.MX8MM and i.MX8MN by using imx_clk_hw_mux2
   - Switch from .round_rate to .determine_rate in clk-divider-gate
   - Fix clock tree update for TF-A controlled clocks for all i.MX8M
   - Add missing M7 core clock for i.MX8MN
   - YAML conversion of rk3399 clock controller binding
   - Removal of GRF dependency for the rk3328/rk3036 pll types
   - Drop CLK_IS_CRITICAL flag from Tegra fuse clk
   - Make CLK_R9A06G032 Kconfig symbol invisible
   - Convert various DT bindings to YAML"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (128 commits)
  dt-bindings: clock: samsung: fix header path in example
  clk: tegra: fix old-style declaration
  clk: qcom: Add SM6350 GCC driver
  MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry
  dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema
  dt-bindings: clock: samsung: convert Exynos AudSS to dtschema
  dt-bindings: clock: samsung: convert Exynos4 to dtschema
  dt-bindings: clock: samsung: convert Exynos3250 to dtschema
  dt-bindings: clock: samsung: convert Exynos542x to dtschema
  dt-bindings: clock: samsung: add bindings for Exynos external clock
  dt-bindings: clock: samsung: convert Exynos5250 to dtschema
  clk: vc5: Add properties for configuring SD/OE behavior
  clk: vc5: Use dev_err_probe
  dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
  dt-bindings: clock: brcm,iproc-clocks: fix armpll properties
  clk: zynqmp: Fix kernel-doc format
  clk: at91: clk-generated: Limit the requested rate to our range
  clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates
  clk: zynqmp: Fix a memory leak
  clk: zynqmp: Check the return type
  ...
</content>
</entry>
<entry>
<title>Merge tag 'mailbox-v5.15' of git://git.linaro.org/landing-teams/working/fujitsu/integration</title>
<updated>2021-09-02T21:12:24+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-09-02T21:12:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=a180eab0b564a9dc149beb0517136ef7129f1260'/>
<id>urn:sha1:a180eab0b564a9dc149beb0517136ef7129f1260</id>
<content type='text'>
Pull mailbox updates from Jassi Brar:

 - mtk:
     - added support for mt8192 and mt8195
     - minor fix regarding address shift

 - qcom:
     - added compatibles for MSM8953, SM6350 and SM6115
     - enable loading IPCC as a module

 - misc:
     - change Altera maintainer
     - fix sti kernel-doc warnings

* tag 'mailbox-v5.15' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: cmdq: add multi-gce clocks support for mt8195
  mailbox: cmdq: add mediatek mailbox support for mt8195
  dt-bindings: gce: add gce header file for mt8195
  dt-bindings: mailbox: add definition for mt8195
  mailbox: qcom-apcs-ipc: Add compatible for MSM8953 SoC
  dt-bindings: mailbox: Add compatible for the MSM8953
  dt-bindings: mailbox: qcom-ipcc: Add compatible for SM6350
  mailbox: qcom: Add support for SM6115 APCS IPC
  dt-bindings: mailbox: qcom: Add SM6115 APCS compatible
  soc: mediatek: cmdq: add address shift in jump
  mailbox: cmdq: add mt8192 support
  dt-binding: gce: add gce header file for mt8192
  MAINTAINERS: Replace Ley Foon Tan as Altera Mailbox maintainer
  mailbox: qcom-ipcc: Enable loading QCOM_IPCC as a module
  mailbox: sti: quieten kernel-doc warnings
</content>
</entry>
<entry>
<title>Merge tag 'devicetree-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux</title>
<updated>2021-09-02T01:34:51+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-09-02T01:34:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=9e5f3ffcf1cb34e7c7beb3f79a96f58536730924'/>
<id>urn:sha1:9e5f3ffcf1cb34e7c7beb3f79a96f58536730924</id>
<content type='text'>
Pull devicetree updates from Rob Herring:

 - Refactor arch kdump DT related code to a common implementation

 - Add fw_devlink tracking for 'phy-handle', 'leds', 'backlight',
   'resets', and 'pwm' properties

 - Various clean-ups to DT FDT code

 - Fix a runtime error for !CONFIG_SYSFS

 - Convert Synopsys DW PCI and derivative binding docs to schemas. Add
   Toshiba Visconti PCIe binding.

 - Convert a bunch of memory controller bindings to schemas

 - Covert eeprom-93xx46, Samsung Exynos TRNG, Samsung Exynos IRQ
   combiner, arm-charlcd, img-ascii-lcd, UniPhier eFuse, Xilinx Zynq
   MPSoC FPGA, Xilinx Zynq MPSoC reset, Mediatek mmsys, Gemini boards,
   brcm,iproc-i2c, faraday,ftpci100, and ks8851 net to DT schema.

 - Extend nvmem bindings to handle bit offsets in unit-addresses

 - Add DT schemas for HiKey 970 PCIe PHY

 - Remove unused ZTE, energymicro,efm32-timer, and Exynos SATA bindings

 - Enable dtc pci_device_reg warning by default

 - Fixes for handling 'unevaluatedProperties' in preparation to enable
   pending support in the tooling for jsonschema 2020-12 draft

* tag 'devicetree-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (78 commits)
  dt-bindings: display: remove zte,vou.txt binding doc
  dt-bindings: hwmon: merge max1619 into trivial devices
  dt-bindings: mtd-physmap: Add 'arm,vexpress-flash' compatible
  dt-bindings: PCI: imx6: convert the imx pcie controller to dtschema
  dt-bindings: Use 'enum' instead of 'oneOf' plus 'const' entries
  dt-bindings: Add vendor prefix for Topic Embedded Systems
  of: fdt: Rename reserve_elfcorehdr() to fdt_reserve_elfcorehdr()
  arm64: kdump: Remove custom linux,usable-memory-range handling
  arm64: kdump: Remove custom linux,elfcorehdr handling
  riscv: Remove non-standard linux,elfcorehdr handling
  of: fdt: Use IS_ENABLED(CONFIG_BLK_DEV_INITRD) instead of #ifdef
  of: fdt: Add generic support for handling usable memory range property
  of: fdt: Add generic support for handling elf core headers property
  crash_dump: Make elfcorehdr address/size symbols always visible
  dt-bindings: memory: convert Samsung Exynos DMC to dtschema
  dt-bindings: devfreq: event: convert Samsung Exynos PPMU to dtschema
  dt-bindings: devfreq: event: convert Samsung Exynos NoCP to dtschema
  kbuild: Enable dtc 'pci_device_reg' warning by default
  dt-bindings: soc: remove obsolete zte zx header
  dt-bindings: clock: remove obsolete zte zx header
  ...
</content>
</entry>
</feed>
