<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/drivers, branch dev-5.10.49-intel</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.10.49-intel</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.10.49-intel'/>
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<updated>2021-07-26T18:53:22+00:00</updated>
<entry>
<title>i2c: aspeed: fix interrupt handling on some abnormal cases</title>
<updated>2021-07-26T18:53:22+00:00</updated>
<author>
<name>Jae Hyun Yoo</name>
<email>jae.hyun.yoo@intel.com</email>
</author>
<published>2021-07-26T18:42:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=15fc5f9458794e52085a58b6734168b6dce0fc73'/>
<id>urn:sha1:15fc5f9458794e52085a58b6734168b6dce0fc73</id>
<content type='text'>
These two exceptional cases were rarely observed in a slave device
reset or in a peer master reset conditions.

1. aspeed-i2c-bus 1e78a480.i2c-bus: irq handled != irq. expected 0x00000030, but was 0x00000020
   when master goes from ASPEED_I2C_MASTER_STOP to
   ASPEED_I2C_MASTER_INACTIVE state due to an
   ASPEED_I2CD_INTR_ABNORMAL event. In this case,
   ASPEED_I2CD_INTR_NORMAL_STOP should be simply ignored without
   printing out the error message.

2. aspeed-i2c-bus 1e78a480.i2c-bus: irq handled != irq. expected 0x00000010, but was 0x00000000
   when master already went to ASPEED_I2C_MASTER_INACTIVE. H/W sends
   one additional ASPEED_I2CD_INTR_NORMAL_STOP event but it's a
   garbage because driver is already in inactive state so filter it
   off from the error message printing out.

Signed-off-by: Jae Hyun Yoo &lt;jae.hyun.yoo@intel.com&gt;
Change-Id: I94794a9612a7e8db445591e490bad6adae0faacf
</content>
</entry>
<entry>
<title>fixup! i2c: Add mux hold/unhold msg types</title>
<updated>2021-07-26T18:22:43+00:00</updated>
<author>
<name>Jae Hyun Yoo</name>
<email>jae.hyun.yoo@intel.com</email>
</author>
<published>2021-07-26T18:13:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=986843a87f9f2c2e2eaf99f3d8432e00d8751dc7'/>
<id>urn:sha1:986843a87f9f2c2e2eaf99f3d8432e00d8751dc7</id>
<content type='text'>
Fixup an unexpected bus holding case caused by a message sending
failure on packet which has a holding message. In case of an error
on sending a message, a bus holding should be immediately released
by itself to prevent a race condition because user space doesn't
send an unhold message when a packet which has hold message fails.
This case was obversed in PLDM stress test which can make intensive
AIC resets so driver was in a severe condition that has lots of
arbitration losses and abnormal stops.

Signed-off-by: Jae Hyun Yoo &lt;jae.hyun.yoo@intel.com&gt;
Change-Id: Ibd169c791d0c24f41932ea676d4e187ddbd3e140
</content>
</entry>
<entry>
<title>mfd: intel-peci-client: Extend MFD cell id with additional parameter</title>
<updated>2021-07-14T17:10:33+00:00</updated>
<author>
<name>Iwona Winiarska</name>
<email>iwona.winiarska@intel.com</email>
</author>
<published>2021-07-02T14:10:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=12438d7847e57486a52105f25239fa424275ced5'/>
<id>urn:sha1:12438d7847e57486a52105f25239fa424275ced5</id>
<content type='text'>
If we're only using CPU number as MFD cell id, we don't have a way to
avoid a collision in case we have multiple adapters able to communicate
with the same CPUs.

[  794.916872] sysfs: cannot create duplicate filename '/bus/platform/devices/peci-cputemp.0'
[  795.452507] intel_peci_client 1-30: Failed to register child devices: -17
[  795.460238] intel_peci_client: probe of 1-30 failed with error -17

To fix this problem, let's use both adapter number and cpu number to
calculate MFD cell id.

Change-Id: If0559a0b629081e6201b4ce93cb8bc649dd2a258
Signed-off-by: Iwona Winiarska &lt;iwona.winiarska@intel.com&gt;
</content>
</entry>
<entry>
<title>ASD Disable JTAG Master controller output when driver is released</title>
<updated>2021-07-14T17:10:33+00:00</updated>
<author>
<name>Ernesto Corona</name>
<email>ernesto.corona@intel.com</email>
</author>
<published>2021-06-02T19:04:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=daee5b9f522896762be5c2423a8dc3d5d92a4f07'/>
<id>urn:sha1:daee5b9f522896762be5c2423a8dc3d5d92a4f07</id>
<content type='text'>
To avoid conflicts with other JTAG hardware probes such as XDP, ASD
must disable JTAG Master controller output when ASD connection is not
in use.

This commit fixes the output disable for AST26xx series which needs
ASPEED_JTAG_CTRL and ASPEED_JTAG_GBLCTRL to be cleared for all SW,
HW1 and HW2 modes.

Test:
1. Run jtag_test
2. Run ASD Sanity(using XDP) - Failed here before
3. Run jtag_test
4. Run ASD Sanity(using ASD)
5. Run ASD Sanity(using XDP) - Failed here before
6. ASD Sanity(using ASD)

Signed-off-by: Ernesto Corona &lt;ernesto.corona@intel.com&gt;
Change-Id: I4f403f4b8412ab96cee195412cc412360845b6d0
</content>
</entry>
<entry>
<title>hwmon: peci: clear time window configuration</title>
<updated>2021-07-14T17:10:33+00:00</updated>
<author>
<name>Zbigniew Lukwinski</name>
<email>zbigniew.lukwinski@linux.intel.com</email>
</author>
<published>2021-05-19T23:33:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=7457b4915fa27af4c06220b2c903d5a2430dcf28'/>
<id>urn:sha1:7457b4915fa27af4c06220b2c903d5a2430dcf28</id>
<content type='text'>
This patch makes time window setting to be cleared when disabling
power capping just like others settings.

Change-Id: I3a5fc9c1eb6a5787d131bf69cc18a5dae94a99f0
Signed-off-by: Zbigniew Lukwinski &lt;zbigniew.lukwinski@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>hwmon: peci: timestamps for sensors correction</title>
<updated>2021-07-14T17:10:33+00:00</updated>
<author>
<name>Zbigniew Lukwinski</name>
<email>zbigniew.lukwinski@linux.intel.com</email>
</author>
<published>2021-05-19T22:55:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=daa38b60c11308c0869d34f337188df8f277211b'/>
<id>urn:sha1:daa38b60c11308c0869d34f337188df8f277211b</id>
<content type='text'>
This patch makes timestaps catching to happen just after PECI
transaction. It makes reading more accurate since PECI request can hang
while waiting in PECI driver queue.

Change-Id: I1a356caa59148a5cebcfcdf89211038bfadb40d3
Signed-off-by: Zbigniew Lukwinski &lt;zbigniew.lukwinski@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>Add chip unique id reading interface</title>
<updated>2021-07-14T17:10:33+00:00</updated>
<author>
<name>Jae Hyun Yoo</name>
<email>jae.hyun.yoo@intel.com</email>
</author>
<published>2020-03-27T21:42:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=afa31118717f755478cbdff0047a6b3bcfddba27'/>
<id>urn:sha1:afa31118717f755478cbdff0047a6b3bcfddba27</id>
<content type='text'>
This commit adds an interface for reading chip unique id value.
Optionally, the id can be encrypted using a dts-supplied hash data.

Signed-off-by: Jae Hyun Yoo &lt;jae.hyun.yoo@intel.com&gt;
Signed-off-by: Vernon Mauery &lt;vernon.mauery@linux.intel.com&gt;
Signed-off-by: Arun P. Mohanan &lt;arun.p.m@linux.intel.com&gt;
Change-Id: Ifd98500ea87b3d40e1738e583e077a74851fae35
</content>
</entry>
<entry>
<title>soc: aspeed: mctp: Reject packets with invalid payload size</title>
<updated>2021-07-14T17:10:33+00:00</updated>
<author>
<name>Iwona Winiarska</name>
<email>iwona.winiarska@intel.com</email>
</author>
<published>2021-05-11T12:45:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=11e00eda4903f1939fdb978e6a6c76136502e187'/>
<id>urn:sha1:11e00eda4903f1939fdb978e6a6c76136502e187</id>
<content type='text'>
When we program TX command register, it requires packet data size in
dwords. Since the aspeed-mctp driver doesn't implement MCTP protocol, it
copies MCTP packet "as it" form userspace and uses size from write()
syscall to program TX command.
If the size from write() doesn't match the payload length in packet PCIe
VDM header, it causes MCTP HW to stop working and we are not able to
reset it without platform power cycle.

To avoid HW issues, let's verify if the data size from write() matches
the payload length in PCIe VDM header.

Signed-off-by: Iwona Winiarska &lt;iwona.winiarska@intel.com&gt;
Change-Id: I6da14babadcc65cb2ba4a2b685495d1baa92c169
</content>
</entry>
<entry>
<title>misc: aspeed: add a raw value setting interface for uart routing</title>
<updated>2021-07-14T17:10:33+00:00</updated>
<author>
<name>Jae Hyun Yoo</name>
<email>jae.hyun.yoo@linux.intel.com</email>
</author>
<published>2021-04-28T16:43:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=8c8b5ba936366a18021193ec301f0214d022af59'/>
<id>urn:sha1:8c8b5ba936366a18021193ec301f0214d022af59</id>
<content type='text'>
This commit adds a raw value setting interface for uart routing
to provide an atomic way of switching the route.

Signed-off-by: Jae Hyun Yoo &lt;jae.hyun.yoo@linux.intel.com&gt;
Change-Id: Id8b80f44f9a503d9f25a692211fc5ec78500ce68
</content>
</entry>
<entry>
<title>Update I3C bus device list</title>
<updated>2021-07-14T17:10:33+00:00</updated>
<author>
<name>Jonathan Doman</name>
<email>jonathan.doman@intel.com</email>
</author>
<published>2021-04-05T16:11:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=4ab708bf2dbf823a7d2edaa69d16fb031416eb88'/>
<id>urn:sha1:4ab708bf2dbf823a7d2edaa69d16fb031416eb88</id>
<content type='text'>
To support communication with NVDIMM controllers, add definitions for
these I3C devices. Each bus now has two definitions for each DIMM slot.
If populated with a DDR5 DIMM, the SPD Hub device will be used to gather
temperature readings. If populated with an NVDIMM, we'll only need to
talk to the controller sitting behind the hub (local device type 1011b),
to read temperature and use the FW mailbox.

This also removes some logic in the I3C driver which restricts use of
certain addresses due to signal integrity paranoia. An NVDIMM controller
in slot 6 of any bus is blocked by this logic, and unfortunately we
don't have any control over the static address scheme used on the SPD
bus, so the restriction must be removed.

Tested:
Probed I3C busses successfully with DIMMs installed in busses 0 and 1:

$ gpioset $(gpiofind FM_SPD_SWITCH_CTRL_N)=1
$ echo 1e7a2000.i3c0 &gt; /sys/bus/platform/drivers/dw-i3c-master/bind
$ echo 1e7a3000.i3c1 &gt; /sys/bus/platform/drivers/dw-i3c-master/bind
$ ls /dev/i3c*
/dev/i3c-0-3c000000000 /dev/i3c-0-3c000000001 /dev/i3c-0-3c000000002
/dev/i3c-0-3c000000003 /dev/i3c-0-3c000000004 /dev/i3c-0-3c000000005
/dev/i3c-0-3c000000006 /dev/i3c-0-3c000000007 /dev/i3c-0-3c000000008
/dev/i3c-0-3c000000009 /dev/i3c-0-3c00000000a /dev/i3c-0-3c00000000b
/dev/i3c-0-3c00000000c /dev/i3c-0-3c00000000d /dev/i3c-0-3c00000000e
/dev/i3c-1-3c000000000 /dev/i3c-1-3c000000001 /dev/i3c-1-3c000000002
/dev/i3c-1-3c000000003 /dev/i3c-1-3c000000004 /dev/i3c-1-3c000000005
/dev/i3c-1-3c000000006 /dev/i3c-1-3c000000007 /dev/i3c-1-3c000000008
/dev/i3c-1-3c000000009 /dev/i3c-1-3c00000000a /dev/i3c-1-3c00000000b
/dev/i3c-1-3c00000000c /dev/i3c-1-3c00000000d /dev/i3c-1-3c00000000e

Change-Id: I016450edad1ed4ec981500f04122976f1647b8ee
Signed-off-by: Jonathan Doman &lt;jonathan.doman@intel.com&gt;
</content>
</entry>
</feed>
