BMC/Intel-BMC/linux.git/drivers/soc, branch dev-5.14-intelIntel OpenBMC Linux kernel source tree (mirror)https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.14-intel2021-10-19T22:10:40+00:00soc: aspeed: mctp: fix a build break2021-10-19T22:10:40+00:00Jae Hyun Yoojae.hyun.yoo@linux.intel.com2021-10-02T02:22:15+00:00urn:sha1:5961fe1c6410a03315731cb88260e85cb4fbd3c7
This commit fixes a build break which is caused by an incompatible
compare function parameter of list_sort() call.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
soc: aspeed: mctp: Clear TX channel and client rings after reset2021-10-19T22:10:40+00:00Iwona Winiarskaiwona.winiarska@intel.com2021-09-01T19:49:29+00:00urn:sha1:b87f274449192833e543718b58053b4ae09447b3
Currently, after TX channel wr_ptr reaches the maximum value, there is
no mechanism to clear it. The driver expects that the HW will make
forward progress, and eventually the buffer will have free space
available. That's not true for some reset scenarios and when this
happens, we may end up with a blocked full channel.
While we could fix it by just adding a trigger after reset, this may
cause userspace to receive unexpected responses for packets that got
stuck in queues during reset.
Let's fix it by flushing both TX channel and client rings.
Note: The barriers are necessary just to enforce ordering between flush
and producing new packets by the clients (we don't want to flush packets
that were sent after reset, just the ones that were sent before it) but
to keep things consistent, introduce helpers for all priv->pcie.bdf
accesses.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
Change-Id: I457a05a6e7f0cb1fd8ce6f2bff6a59b166d32149
soc: aspeed: lpc-sio: add SMI event triggering support2021-10-19T22:10:39+00:00Jae Hyun Yoojae.hyun.yoo@intel.com2021-08-12T22:40:54+00:00urn:sha1:c2b347a07158a30215720ad0ab9f109e4b449189
Add SMI event triggering support.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Change-Id: I711b5642a654e671a2d97d3079e3a1a055d400a0
Add chip unique id reading interface2021-10-19T22:10:39+00:00Jae Hyun Yoojae.hyun.yoo@intel.com2020-03-27T21:42:05+00:00urn:sha1:82b4607830605d3c39994df300a8f74255668bac
This commit adds an interface for reading chip unique id value.
Optionally, the id can be encrypted using a dts-supplied hash data.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com>
Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
Change-Id: Ifd98500ea87b3d40e1738e583e077a74851fae35
soc: aspeed: mctp: Reject packets with invalid payload size2021-10-19T22:10:39+00:00Iwona Winiarskaiwona.winiarska@intel.com2021-05-11T12:45:41+00:00urn:sha1:f9633121f4051fe22a479864a18997ef9b3e25ec
When we program TX command register, it requires packet data size in
dwords. Since the aspeed-mctp driver doesn't implement MCTP protocol, it
copies MCTP packet "as it" form userspace and uses size from write()
syscall to program TX command.
If the size from write() doesn't match the payload length in packet PCIe
VDM header, it causes MCTP HW to stop working and we are not able to
reset it without platform power cycle.
To avoid HW issues, let's verify if the data size from write() matches
the payload length in PCIe VDM header.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
Change-Id: I6da14babadcc65cb2ba4a2b685495d1baa92c169
mailbox: ioctl to fetch mailbox size2021-10-19T22:10:38+00:00Arun P. Mohananarun.p.m@linux.intel.com2021-03-18T10:18:09+00:00urn:sha1:77e17b1e75532fad41d20a04429335bc5f8242e9
The size of mailbox differ from AST2500, AST2600 A0 and A1. Add an ioctl
support to fetch the mailbox size.
Tested:
Verfied ioctl call returns mailbox size as expected.
Change-Id: I4e261aaf8aa3fb108d6ad152d30a17b114d70ccd
Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
soc: aspeed: Miscellaneous control interfaces2021-10-19T22:10:37+00:00Andrew Jefferyandrew@aj.id.au2018-04-11T06:34:10+00:00urn:sha1:8eaa1391bca297010b9d0dbf0fc4e4d2642c235e
The ASPEED BMC SoCs have many knobs and switches that are sometimes
design-specific and often defy any approach to unify them under an
existing subsystem.
Add a driver to translate a devicetree table into sysfs entries to
expose bits and fields for manipulation from userspace. This encompasses
concepts from scratch registers to boolean conditions to enable or
disable host interface features.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
soc: aspeed: mctp: Export function used to read BDF2021-10-19T22:10:37+00:00Iwona Winiarskaiwona.winiarska@intel.com2021-01-28T21:31:31+00:00urn:sha1:8414dc5fd37b29d3d4a2ec5cfe2a06bfccc53fbd
Recently, aspeed-mctp driver functionality was extended to store BDF
values for already discovered MCTP endpoints on PCIe bus.
Let's expose kernel API to read BDF based on endpoint ID.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
Enable mailbox interrupts2021-10-19T22:10:37+00:00Yong Liyong.b.li@linux.intel.com2021-01-29T10:11:25+00:00urn:sha1:be4fc3a8ac4afce3ccd5c8d8653c49375e84fc47
Support interrupt generation for both 16 and 32 mailbox registers.
Tested:
After applied this patch, write the mailbox registers from BIOS side,
the misc manager can capture the new mailbox data.
Signed-off-by: Yong Li <yong.b.li@linux.intel.com>
soc: aspeed: aspeed-espi-slave: fix SUS_WARN handling logic2021-10-19T22:10:36+00:00Jae Hyun Yoojae.hyun.yoo@linux.intel.com2020-10-20T22:33:56+00:00urn:sha1:825445d77df85709ddb98d79ee5a8d655e1e907d
This commit fixes SUS_WARN handling as dual-edge detection mode
to support deepsx entry event properly.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>