BMC/Intel-BMC/linux.git/drivers/soc, branch dev-5.10.49-intelIntel OpenBMC Linux kernel source tree (mirror)https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.10.49-intel2021-07-14T17:10:33+00:00Add chip unique id reading interface2021-07-14T17:10:33+00:00Jae Hyun Yoojae.hyun.yoo@intel.com2020-03-27T21:42:05+00:00urn:sha1:afa31118717f755478cbdff0047a6b3bcfddba27
This commit adds an interface for reading chip unique id value.
Optionally, the id can be encrypted using a dts-supplied hash data.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com>
Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
Change-Id: Ifd98500ea87b3d40e1738e583e077a74851fae35
soc: aspeed: mctp: Reject packets with invalid payload size2021-07-14T17:10:33+00:00Iwona Winiarskaiwona.winiarska@intel.com2021-05-11T12:45:41+00:00urn:sha1:11e00eda4903f1939fdb978e6a6c76136502e187
When we program TX command register, it requires packet data size in
dwords. Since the aspeed-mctp driver doesn't implement MCTP protocol, it
copies MCTP packet "as it" form userspace and uses size from write()
syscall to program TX command.
If the size from write() doesn't match the payload length in packet PCIe
VDM header, it causes MCTP HW to stop working and we are not able to
reset it without platform power cycle.
To avoid HW issues, let's verify if the data size from write() matches
the payload length in PCIe VDM header.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
Change-Id: I6da14babadcc65cb2ba4a2b685495d1baa92c169
mailbox: ioctl to fetch mailbox size2021-07-14T17:10:33+00:00Arun P. Mohananarun.p.m@linux.intel.com2021-03-18T10:18:09+00:00urn:sha1:e296d7049f4e899db4fb4918c8f4c4831bed3b1d
The size of mailbox differ from AST2500, AST2600 A0 and A1. Add an ioctl
support to fetch the mailbox size.
Tested:
Verfied ioctl call returns mailbox size as expected.
Change-Id: I4e261aaf8aa3fb108d6ad152d30a17b114d70ccd
Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
soc: aspeed: Miscellaneous control interfaces2021-07-14T17:07:00+00:00Andrew Jefferyandrew@aj.id.au2018-04-11T06:34:10+00:00urn:sha1:043ee67ff32bb430fb483b7f72e34b2e1f68c93e
The ASPEED BMC SoCs have many knobs and switches that are sometimes
design-specific and often defy any approach to unify them under an
existing subsystem.
Add a driver to translate a devicetree table into sysfs entries to
expose bits and fields for manipulation from userspace. This encompasses
concepts from scratch registers to boolean conditions to enable or
disable host interface features.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
soc: aspeed: mctp: Export function used to read BDF2021-07-14T17:05:11+00:00Iwona Winiarskaiwona.winiarska@intel.com2021-01-28T21:31:31+00:00urn:sha1:43b691f5a9b9694f6fbc954fc42bb95100b8c0b8
Recently, aspeed-mctp driver functionality was extended to store BDF
values for already discovered MCTP endpoints on PCIe bus.
Let's expose kernel API to read BDF based on endpoint ID.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
Enable mailbox interrupts2021-07-14T17:05:06+00:00Yong Liyong.b.li@linux.intel.com2021-01-29T10:11:25+00:00urn:sha1:d2f75c4e5cabf90dc8980b8f5e83dc6bf9000039
Support interrupt generation for both 16 and 32 mailbox registers.
Tested:
After applied this patch, write the mailbox registers from BIOS side,
the misc manager can capture the new mailbox data.
Signed-off-by: Yong Li <yong.b.li@linux.intel.com>
Move Aspeed eSPI driver to soc/aspeed tree2021-07-14T17:04:18+00:00Jae Hyun Yoojae.hyun.yoo@intel.com2021-01-14T23:06:08+00:00urn:sha1:57daf90aed682e2979e90d892d25b0c971ed35c7
This commit moves Aspeed eSPI driver from misc to soc/aspeed tree
to make correct probing order for LPC and eSPI driver. Since LPC
runs over eSPI, eSPI driver should be registered ahead of LPC
driver.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
soc: aspeed: mctp: Register peci_mctp device2021-07-14T17:04:18+00:00Iwona Winiarskaiwona.winiarska@intel.com2020-12-06T13:18:57+00:00urn:sha1:1e8e06a03bae097ed47bf5fb840925edca8ae93f
Now that it is possible to send PECI frames via aspeed-mctp driver,
let's add aspeed-peci-mctp node to allow bind peci-mctp-aspeed adapter
driver.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
soc: aspeed: mctp: Fix TX hangs and optimize TX logic2021-07-14T17:04:18+00:00Andrzej Kacprowskiandrzej.kacprowski@linux.intel.com2020-12-30T12:25:34+00:00urn:sha1:a19efc3bb09e4eb3798883c6598ca523fb852954
Currently driver submits 1 (or rarely more than 1) packet then
waits until HW signals transmission completion before sending
more packets. This logic requires interrupt after each packet,
aspeed_mctp_tx_tasklet() is invoked twice per packet.
New logic uses TX ring correctly, packets are added to the end of
circular ring buffer. The driver does not have to wait for HW to
complete transmission of enqueued packets before adding more packets
to TX queue. Interrupt is generated only if TX ring if full.
This change significantly improves packet transmission performance:
PECI GetTemp command takes ~25us instead of ~30us.
This change also fixes sporadic TX hangs during host reboot seen
with current driver.
Signed-off-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com>
soc: aspeed: mctp: Update source EID in TX packets2021-07-14T17:04:18+00:00Andrzej Kacprowskiandrzej.kacprowski@linux.intel.com2020-12-28T12:03:39+00:00urn:sha1:a35ce3881bcf691d60c6f9e53bd540b81d6fd71e
If self EID is known then the driver updates source EID in
MCTP header of sent packets. For MCTP control packets the
source EID is not updated as it may disrupt MCTP discovery flow.
Self EID is determined from list of known endpoints provided
by ASPEED_MCTP_IOCTL_SET_EID_INFO IOCTL.
Signed-off-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com>