BMC/Intel-BMC/linux.git/drivers/soc/mediatek, branch dev-5.15-intel

soc: mediatek: pm-domains: Add wakeup capacity support in power domain

2022-04-08T12:23:18+00:00

[ Upstream commit ac0ca395543af061f7ad77afcda0afb323d82468 ] Due to some power domain needs to keep on for wakeup in system suspend, so add GENPD_FLAG_ACTIVE_WAKEUP support in Mediatek power domain driver. Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") Signed-off-by: Chun-Jie Chen Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220130012104.5292-3-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger Signed-off-by: Sasha Levin

Revert "ASoC: mediatek: Check for error clk pointer"

2022-02-08T17:34:06+00:00

This reverts commit 38accfd85e41b7ca547c5a7d4866bbc1462950cb which is commit 9de2b9286a6dd16966959b3cb34fc2ddfd39213e upstream With this patch in the tree, Chromebooks running the affected hardware no longer boot. Bisect points to this patch, and reverting it fixes the problem. An analysis of the code with this patch applied shows: ret = init_clks(pdev, clk); if (ret) return ERR_PTR(ret); ... for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) { struct clk *c = clk[data->clk_id[j]]; if (IS_ERR(c)) { dev_err(&pdev->dev, "%s: clk unavailable\n", data->name); return ERR_CAST(c); } scpd->clk[j] = c; } Not all clocks in the clk_names array have to be present. Only the clocks in the data->clk_id array are actually needed. The code already checks if the required clocks are available and bails out if not. The assumption that all clocks have to be present is wrong, and commit 9de2b9286a6d needs to be reverted. Fixes: 9de2b9286a6d ("ASoC: mediatek: Check for error clk pointer") Cc: Jiasheng Jiang Cc: Mark Brown Cc: James Liao Cc: Kevin Hilman Cc: Matthias Brugger Cc: Daniel Golle Link: https://lore.kernel.org/lkml/20220205014755.699603-1-linux@roeck-us.net/ Signed-off-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman

ASoC: mediatek: Check for error clk pointer

2022-01-27T10:04:16+00:00

[ Upstream commit 9de2b9286a6dd16966959b3cb34fc2ddfd39213e ] Yes, you are right and now the return code depending on the init_clks(). Fixes: 6078c651947a ("soc: mediatek: Refine scpsys to support multiple platform") Signed-off-by: Jiasheng Jiang Link: https://lore.kernel.org/r/20211222015157.1025853-1-jiasheng@iscas.ac.cn Signed-off-by: Mark Brown Signed-off-by: Sasha Levin

soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing

2021-08-06T14:43:23+00:00

The UFOE (data compression engine) component needs to be enabled to have the imgtec gpu driver working. If we don't enable it we see a black screen. Looks like when we switched to use and array for setting the routing registers in commit 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers") we missed to add this component in the new routing table, it was present before that commit, so fix it by adding this component in the mt8173 routing table. Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers") Signed-off-by: Enric Balletbo i Serra Tested-by: Eizan Miyamoto Cc: Link: https://lore.kernel.org/r/20210625062448.3462177-1-enric.balletbo@collabora.com [mb: taking into account mask value] Signed-off-by: Matthias Brugger

soc: mediatek: mmsys: add MT8365 support

2021-08-06T14:43:23+00:00

Add DSI mmsys connections for the MT8365 SoC. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20210519161847.3747352-3-fparent@baylibre.com [mb: take the mask field into account] Signed-off-by: Matthias Brugger

soc: mmsys: mediatek: add mask to mmsys routes

2021-08-04T17:05:46+00:00

SOUT has many bits and need to be cleared before set new value. Write only could do the clear, but for MOUT, it clears bits that should not be cleared. So use a mask to reset only the needed bits. this fixes HDMI issues on MT7623/BPI-R2 since 5.13 Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers") Signed-off-by: Frank Wunderlich Signed-off-by: CK Hu Reviewed-by: Chun-Kuang Hu Reviewed-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20210729070549.5514-1-linux@fw-web.de Signed-off-by: Matthias Brugger

soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD

2021-07-12T10:26:29+00:00

The mfg_async power domain in mt8173 is used to power up imgtec gpu. This domain requires the da9211 regulator to be enabled before the power domain can be enabled successfully. Signed-off-by: Bilal Wasim Signed-off-by: Enric Balletbo i Serra Reviewed-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20210701114012.RESEND.2.I2e1bf1b589f9138ba6f89791ed9f1e9f3ddd0a5d@changeid Signed-off-by: Matthias Brugger

soc: mediatek: pm-domains: Use correct mask for bus_prot_clr

2021-07-12T10:26:28+00:00

When "bus_prot_reg_update" is true, the driver should use INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus protection. However, the driver does not use this mask for clearing bus protection which causes failure when booting the imgtec gpu. Corrected and tested with mt8173 chromebook. Signed-off-by: Bilal Wasim Signed-off-by: Enric Balletbo i Serra Reviewed-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20210701114012.RESEND.1.I27436c29c3bede46dcf86df696f48683662d1ec1@changeid Signed-off-by: Matthias Brugger

soc: mediatek: pwrap: add pwrap driver for MT8195 SoC

2021-06-03T17:41:26+00:00

MT8195 are highly integrated SoC and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Henry Chen Link: https://lore.kernel.org/r/20210602112050.12338-3-james.lo@mediatek.com Signed-off-by: Matthias Brugger

soc: mtk-pm-domains: Fix the clock prepared issue

2021-06-02T11:53:31+00:00

In this new power domain driver, when adding one power domain it will prepare the dependent clocks at the same. So we only do clk_bulk_enable/disable control during power ON/OFF. When system suspend, the pm runtime framework will forcely power off power domains. However, the dependent clocks are disabled but kept prepared. In MediaTek clock drivers, PLL would be turned ON when we do clk_bulk_prepare control. Clock hierarchy: PLL --> DIV_CK --> CLK_MUX (may be dependent clocks) --> SUBSYS_CG (may be dependent clocks) It will lead some unexpected clock states during system suspend. This patch will fix by doing prepare_enable/disable_unprepare on dependent clocks at the same time while we are going to power on/off any power domain. Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") Signed-off-by: Weiyi Lu Signed-off-by: Hsin-Yi Wang Reviewed-by: chun-jie.chen Reviewed-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20210601035905.2970384-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger