BMC/Intel-BMC/linux.git/drivers/pinctrl, branch dev-5.14-intel

pinctrl: aspeed: g6: modify RMII4 group

2021-10-19T22:10:38+00:00

Intel doesn't use transmit clock output of RMII4 module so this commit customize RMII4 pin ctrl group by removing the F24 pin setting from RMII4. This is a downstream customization. Do not upstream it. Signed-off-by: Jae Hyun Yoo

Allow monitoring of power control input GPIOs

2021-10-19T22:10:29+00:00

The pass-through input GPIOs cannot be monitored because when requested, pass-through is disabled which causes a change on the pass-through output. The SIO GPIOs cannot be monitored because when requested, the request is rejected based on the value of the ACPI strap. This change removes the register check condition from the pass- through and desired SIO GPIOs so they can be requsted and monitored from power control. Tested: For pass-through, I used gpioset to hold a request on the input GPIOs and confirmed that pass-through remained enabled. For SIO, I used gpioget to confirm that I can successfully request and read the GPIO value. Signed-off-by: Jason M. Bills

Enable pass-through on GPIOE1 and GPIOE3 free

2021-10-19T22:10:29+00:00

This change adds a gpio_disable_free() implementation that checks if the GPIO being freed is GPIOE1 (33) or GPIOE3 (35) and will re-enable the pass-through mux. Tested: Requested GPIOs 33 and 35 and used devmem to check that pass-through was disabled. Then freed them and checked that pass-through was enabled again. Signed-off-by: Jason M. Bills

Merge tag 'v5.14.11' into dev-5.14

2021-10-11T05:22:51+00:00

This is the 5.14.11 stable release Signed-off-by: Joel Stanley

pinctrl: qcom: spmi-gpio: correct parent irqspec translation

2021-10-07T05:53:03+00:00

[ Upstream commit d36a97736b2cc9b13db0dfdf6f32b115ec193614 ] pmic_gpio_child_to_parent_hwirq() and gpiochip_populate_parent_fwspec_fourcell() translate a pinctrl- spmi-gpio irqspec to an SPMI controller irqspec. When they do this, they use a fixed SPMI slave ID of 0 and a fixed GPIO peripheral offset of 0xC0 (corresponding to SPMI address 0xC000). This translation results in an incorrect irqspec for secondary PMICs that don't have a slave ID of 0 as well as for PMIC chips which have GPIO peripherals located at a base address other than 0xC000. Correct this issue by passing the slave ID of the pinctrl-spmi- gpio device's parent in the SPMI controller irqspec and by calculating the peripheral ID base from the device tree 'reg' property of the pinctrl-spmi-gpio device. Signed-off-by: David Collins Signed-off-by: satya priya Fixes: ca69e2d165eb ("qcom: spmi-gpio: add support for hierarchical IRQ chip") Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/1631798498-10864-2-git-send-email-skakit@codeaurora.org Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

Merge tag 'v5.14.6' into dev-5.14

2021-09-22T00:13:12+00:00

This is the 5.14.6 stable release

pinctrl: single: Fix error return code in pcs_parse_bits_in_pinctrl_entry()

2021-09-18T11:43:30+00:00

[ Upstream commit d789a490d32fdf0465275e3607f8a3bc87d3f3ba ] Fix to return -ENOTSUPP instead of 0 when PCS_HAS_PINCONF is true, which is the same as that returned in pcs_parse_pinconf(). Fixes: 4e7e8017a80e ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") Reported-by: Hulk Robot Signed-off-by: Zhen Lei Link: https://lore.kernel.org/r/20210722033930.4034-2-thunder.leizhen@huawei.com Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: samsung: Fix pinctrl bank pin count

2021-09-18T11:43:27+00:00

[ Upstream commit 70115558ab02fe8d28a6634350b3491a542aaa02 ] Commit 1abd18d1a51a ("pinctrl: samsung: Register pinctrl before GPIO") changes the order of GPIO and pinctrl registration: now pinctrl is registered before GPIO. That means gpio_chip->ngpio is not set when samsung_pinctrl_register() called, and one cannot rely on that value anymore. Use `pin_bank->nr_pins' instead of `pin_bank->gpio_chip.ngpio' to fix mentioned inconsistency. Fixes: 1abd18d1a51a ("pinctrl: samsung: Register pinctrl before GPIO") Signed-off-by: Jaehyoung Choi Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20210730192905.7173-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sasha Levin

pinctrl: armada-37xx: Correct PWM pins definitions

2021-09-18T11:43:26+00:00

[ Upstream commit baf8d6899b1e8906dc076ef26cc633e96a8bb0c3 ] The PWM pins on North Bridge on Armada 37xx can be configured into PWM or GPIO functions. When in PWM function, each pin can also be configured to drive low on 0 and tri-state on 1 (LED mode). The current definitions handle this by declaring two pin groups for each pin: - group "pwmN" with functions "pwm" and "gpio" - group "ledN_od" ("od" for open drain) with functions "led" and "gpio" This is semantically incorrect. The correct definition for each pin should be one group with three functions: "pwm", "led" and "gpio". Change the "pwmN" groups to support "led" function. Remove "ledN_od" groups. This cannot break backwards compatibility with older device trees: no device tree uses it since there is no PWM driver for this SOC yet. Also "ledN_od" groups are not even documented. Fixes: b835d6953009 ("pinctrl: armada-37xx: swap polarity on LED group") Signed-off-by: Marek Behún Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210719112938.27594-1-kabel@kernel.org Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: ingenic: Fix bias config for X2000(E)

2021-09-18T11:43:21+00:00

commit 7261851e938f4b0fe8c0f5a8e627ae90e1ba9875 upstream. The ingenic_set_bias() function's "bias" argument is not a "enum pin_config_param", so its value should not be compared against values of that enum. This should fix the bias config not working on the X2000(E) SoCs. Fixes: 943e0da15370 ("pinctrl: Ingenic: Add pinctrl driver for X2000.") Cc: # v5.12 Signed-off-by: Paul Cercueil Tested-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/20210717174836.14776-2-paul@crapouillou.net Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman