Intel OpenBMC Linux kernel source tree (mirror) https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.6 2016-07-12T10:03:22+00:00 2016-07-12T10:03:22+00:00 Joel Stanley joel@jms.id.au 2016-07-12T10:03:22+00:00 urn:sha1:a9bd31fd2347046978c802397ed03e62496fd3d8 This is the 4.6.4 stable release 2016-06-24T17:22:03+00:00 hongkun.cao hongkun.cao@mediatek.com 2016-05-21T07:23:39+00:00 urn:sha1:a958e05dfbbda33ed17bd0d82f5a32f52af49ab5 commit 5edf673d07fdcb6498be24914f3f38f8d8843199 upstream. When a dual-edge irq is triggered, an incorrect irq will be reported on condition that the external signal is not stable and this incorrect irq has been registered. Correct the register offset. Signed-off-by: Hongkun Cao <hongkun.cao@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2016-06-08T19:34:29+00:00 Joel Stanley joel@jms.id.au 2016-06-08T19:34:29+00:00 urn:sha1:cd8f876ccf2f53282b100fd11ed339e7c495d936 This is the 4.6.2 stable release Signed-off-by: Joel Stanley <joel@jms.id.au> 2016-06-08T01:23:38+00:00 Andrew Jeffery andrew@aj.id.au 2016-04-20T01:54:17+00:00 urn:sha1:ade217987b4122e81f0ec9569343a1655b417096 commit 71324fdc72ef0163e57631aa814a9a81e9e4770b upstream. The range is registered into a linked list which can be referenced throughout the lifetime of the driver. Ensure the range's memory is useful for the same lifetime by adding it to the driver's private data structure. The bug was introduced in the driver's initial commit, which was present in v3.10. Fixes: f0b9a7e521fa ("pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2016-06-03T20:52:08+00:00 Andrew Jeffery andrew@aj.id.au 2016-05-26T07:05:11+00:00 urn:sha1:fa5a40957c22f7e3c9be4b4c7dc0eeb33a51e564 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> 2016-06-03T20:52:06+00:00 Joel Stanley joel@jms.id.au 2016-05-25T07:23:23+00:00 urn:sha1:fdf8e8d8dbd742333d4d9467306c241236e2898b Signed-off-by: Joel Stanley <joel@jms.id.au> 2016-06-03T20:52:06+00:00 Andrew Jeffery andrew@aj.id.au 2016-05-25T06:06:51+00:00 urn:sha1:b6f37d5c7319b427f962feaada0bcbb8cfd6cd59 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> 2016-06-03T20:52:02+00:00 Andrew Jeffery andrew@aj.id.au 2016-05-24T06:14:29+00:00 urn:sha1:87229d4e268275f16e33204b3f70c4df05363388 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> 2016-06-03T20:52:01+00:00 Andrew Jeffery andrew@aj.id.au 2016-03-24T07:06:08+00:00 urn:sha1:93504dd9f16c3314d16e76800edf444c658aff24 Leverage the framework added previously to define a subset of pins required to boot the chip. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> 2016-06-03T20:52:01+00:00 Andrew Jeffery andrew@aj.id.au 2016-03-24T07:06:08+00:00 urn:sha1:b6461561b1ee4243604f7f9e69e7069f3a7b1f77 Add pinctrl/pinmux support for the Aspeed SoCs. Configuration of the Aspeed SoCs is somewhat intricate: Enabling functions can involve writes of multiple bits to multiple registers, and signals provided by a pin are determined on a priority basis. That is, without care, it's possible to configure a function in the mux and to not gain expected functionality. Note that this doesn't implement the pinctrl/pinmux/pinconf for any particular SoC, just adds the framework to enable defining the features. Signed-off-by: Andrew Jeffery <andrew@aj.id.au>