BMC/Intel-BMC/linux.git/drivers/pinctrl/aspeed, branch dev-5.3

pinctrl: aspeed: Improve debug output

2019-10-22T22:58:23+00:00

We need to iterate over each pin in a group for a function and disable higher priority mux configurations on the pin before finally muxing the relevant function's signal. With the current debug output it is hard to track what register output is relevant to which operation, so break up the actions in the debug output by providing some more context. Before: [ 5.446656] aspeed-g6-pinctrl 1e6e2000.syscon:pinctrl: request pin 37 (B26) for 1e780000.gpio:341 [ 5.447377] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.447854] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.448340] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 After: [ 5.298053] Muxing pin 37 for GPIO [ 5.298294] Disabling signal NRI4 for NRI4 [ 5.298593] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.298983] Disabling signal RGMII4RXD1 for RGMII4 [ 5.299309] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.299694] Disabling signal RMII4RXD1 for RMII4 [ 5.300014] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.300396] Enabling signal GPIOE5 for GPIOE5 [ 5.300687] Muxed pin 37 as GPIOE5 OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed-g6: Fix LPC/eSPI mux configuration

2019-10-22T22:58:23+00:00

Early revisions of the AST2600 datasheet are conflicted about the state of the LPC/eSPI strapping bit (SCU510[6]). Conversations with ASPEED determined that the reference pinmux configuration tables were in error and the SCU documentation contained the correct configuration. Update the driver to reflect the state described in the SCU documentation. OpenBMC-Staging-Count: 1 Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively

2019-10-22T22:58:22+00:00

Signal descriptors can represent multi-bit bitfields and so have explicit "enable" and "disable" states. However many descriptor instances only describe a single bit, and so the SIG_DESC_SET() macro is provides an abstraction for the single-bit cases: Its expansion configures the "enable" state to set the bit and "disable" to clear. SIG_DESC_CLEAR() was introduced to provide a similar single-bit abstraction for for descriptors to clear the bit of interest. However its behaviour was defined as the literal inverse of SIG_DESC_SET() - the impact is the bit of interest is set in the disable path. This behaviour isn't intuitive and doesn't align with how we want to use the macro in practice, so make it clear the bit for both the enable and disable paths. OpenBMC-Staging-Count: 1 (cherry-picked from commit c136d4c71f755a189fe13a0cd4f3e8f538dda567) Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed-g6: Add AST2600 pinconf support

2019-09-26T14:20:33+00:00

The AST2600 pinconf is a little different from previous generations of ASPEED BMC SoCs in terms of architecture. The pull-down setting is per-pin setting now, and drive-strength support 4 kind of value (e.g. 4ma, 8ma, 12ma, 16ma). OpenBMC-Staging-Count: 1 Signed-off-by: Johnny Huang [AJ: Trim unused pinctrl register macros] Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed: Use masks to describe pinconf bitfields

2019-09-26T14:20:30+00:00

Since some of the AST2600 pinconf setting are not just single bit, modified aspeed_pin_config @bit to @mask and add @mask to aspeed_pin_config_map to support configuring multiple bits. OpenBMC-Staging-Count: 1 Signed-off-by: Johnny Huang [AJ: Tweak commit message] Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed: Move aspeed_pin_config_map to separate source file

2019-09-26T14:20:27+00:00

The AST2600 pinconf differs from the 2400 and 2500, aspeed_pin_config_map should define separately, and add @confmaps and @nconfmaps to aspeed_pinctrl_data structure for that change. OpenBMC-Staging-Count: 1 Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper

2019-09-26T14:20:24+00:00

This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. OpenBMC-Staging-Count: 1 Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed-g6: Add support for the AST2600 USB pinmux

2019-09-26T14:20:20+00:00

AST2600 has two USB ports, A, B: Port A supports 4 distinct modes: 1. PCIe EHCI to Hub 2. Hub to PHY 3. BMC EHCI to PHY 4. PCIe EHCI to PHY Port B support 3 modes: 1. USB1.1 HID controller 2. USB2.0 Device controller 3. BMC EHCI port2 Implement pinmux support by mapping each ports' functions onto a single pin group for each port. OpenBMC-Staging-Count: 1 Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed-g6: Add AST2600 I3C1 and I3C2 pinmux config

2019-09-26T14:20:18+00:00

These pins only expose a single function but are not fixed-function as their I3C capability can be disabled. OpenBMC-Staging-Count: 1 Signed-off-by: Johnny Huang [AJ: Tweak commit message, sort pins list] Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups

2019-09-26T14:20:15+00:00

AST2600 EMMC support 3 types DAT bus sizes (1, 4 and 8-bit), corresponding to 3 groups: EMMCG1, EMMCG4 and EMMCG8 OpenBMC-Staging-Count: 1 Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley