BMC/Intel-BMC/linux.git/drivers/pinctrl/aspeed, branch dev-5.2

pinctrl: aspeed: Fix spurious mux failures on the AST2500

2019-08-29T07:24:08+00:00

Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") was determined to be a partial fix to the problem of acquiring the LPC Host Controller and GFX regmaps: The AST2500 pin controller may need to fetch syscon regmaps during expression evaluation as well as when setting mux state. For example, this case is hit by attempting to export pins exposing the LPC Host Controller as GPIOs. An optional eval() hook is added to the Aspeed pinmux operation struct and called from aspeed_sig_expr_eval() if the pointer is set by the SoC-specific driver. This enables the AST2500 to perform the custom action of acquiring its regmap dependencies as required. John Wang tested the fix on an Inspur FP5280G2 machine (AST2500-based) where the issue was found, and I've booted the fix on Witherspoon (AST2500) and Palmetto (AST2400) machines, and poked at relevant pins under QEMU by forcing mux configurations via devmem before exporting GPIOs to exercise the driver. OpenBMC-Staging-Count: 1 Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Fixes: 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") Reported-by: John Wang Tested-by: John Wang Signed-off-by: Andrew Jeffery

pinctrl: aspeed-g6: Add EMMC pin group

2019-08-22T13:39:13+00:00

The EMMC group enables the 8-bit data bus for eMMC flashes. To enable, use the following node: pinctrl_emmc_default: pinctrl_emmc { function = "SD3"; groups = "EMMC"; }; The replaced functions and groups escaped refactoring I did to other areas before I sent out the initial series for the binding and driver. Removed functions and groups: * SD3DAT4 * SD3DAT5 * SD3DAT6 * SD3DAT7 Added group: * EMMC OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed-g6: Fix mislabeled PWM groups and functions

2019-08-22T13:39:13+00:00

Initial revisions of the datasheet incorrectly described the PWM groups and functions. Particularly, PWM8 only has one pin group associated with it and PWM16 exists. OpenBMC-Staging-Count: 1 Reported-by: Johnny Huang Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed-g6: Fix I2C14 function name typo

2019-08-22T13:39:12+00:00

The pin function was accidentally named after the signal. OpenBMC-Staging-Count: 1 Reported-by: Johnny Huang Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed: Add AST2600 pinmux support

2019-08-22T13:39:12+00:00

The AST2600 pinmux is fairly similar to the previous generations of ASPEED BMC SoCs in terms of architecture, though differ in some of the design details. The complexity of the pin expressions is largely reduced (e.g. there are no-longer signals with multiple expressions muxing them to the associated pin), and there are now signals and buses with multiple pin groups. The driver implements pinmux support for all 244 GPIO-capable pins plus a further four pins that are not GPIO capable but which expose multiple signals. pinconf will be implemented in a follow-up patch. The implementation has been smoke-tested under qemu, and run on hardware by ASPEED. Debugged-by: Johnny Huang Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20190711041942.23202-7-andrew@aj.id.au Signed-off-by: Linus Walleij (cherry picked from commit 2eda1cdec49f8ae7878e60d1b06bd8157a95424f) [arj: squash in patch 21b2920fb587 ("pinctrl: aspeed: g6: Remove const specifier from aspeed_g6_sig_expr_set's ctx parameter")] Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed: Add SIG_DESC_CLEAR() helper

2019-08-22T13:39:12+00:00

The complement of SIG_DESC_SET(). Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20190729055604.13239-6-andrew@aj.id.au Signed-off-by: Linus Walleij (cherry picked from commit 86392fac9a9c92f36c0a422a3075865a0fe959f9) Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed: Add multiple pin group support for functions

2019-08-22T13:39:12+00:00

The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij (cherry picked from commit e7a96b0b7d1669e95aa77c007e71e3c88c531cc4) Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed: Add PIN_DECL_3() helper

2019-08-22T13:39:12+00:00

This case is common in the AST2600, so add to the collection. Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20190729055604.13239-4-andrew@aj.id.au Signed-off-by: Linus Walleij (cherry picked from commit 27d1f73670774e3ea3e304f989f0e1176b57cd7c) Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed: Rename pin declaration macros

2019-08-22T13:39:12+00:00

Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij (cherry picked from commit 7b38897081666532b434e067bdfa85789f42fa4e) Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley

pinctrl: aspeed: Make aspeed_pinmux_ips static

2019-08-22T13:39:12+00:00

Fix sparse warning: drivers/pinctrl/aspeed/pinmux-aspeed.c:8:12: warning: symbol 'aspeed_pinmux_ips' was not declared. Should it be static? Reported-by: Hulk Robot Signed-off-by: YueHaibing Link: https://lore.kernel.org/r/20190711142457.37028-1-yuehaibing@huawei.com Reviewed-by: Andrew Jeffery Signed-off-by: Linus Walleij (cherry picked from commit 8c4407de3be44c2a0ec3e316cd3e4a711bc2aaba) Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley