BMC/Intel-BMC/linux.git/drivers/pinctrl/aspeed, branch dev-5.10-intel

fixup! SGPIO DT and pinctrl fixup

2021-09-13T16:10:31+00:00

This reverts commit 6d512838ba348d7bc7989102ddd56cfdb48c85ee to use upstream sgpio driver. Signed-off-by: Jae Hyun Yoo

pinctrl: aspeed: g6: modify RMII4 group

2021-08-02T16:04:00+00:00

Intel doesn't use transmit clock output of RMII4 module so this commit customize RMII4 pin ctrl group by removing the F24 pin setting from RMII4. This is a downstream customization. Do not upstream it. Signed-off-by: Jae Hyun Yoo

SGPIO DT and pinctrl fixup

2021-08-02T16:04:00+00:00

This commit fixes DT and pinctrl for SGPIO use. Signed-off-by: Vernon Mauery Signed-off-by: Jae Hyun Yoo

Allow monitoring of power control input GPIOs

2021-08-02T16:04:00+00:00

The pass-through input GPIOs cannot be monitored because when requested, pass-through is disabled which causes a change on the pass-through output. The SIO GPIOs cannot be monitored because when requested, the request is rejected based on the value of the ACPI strap. This change removes the register check condition from the pass- through and desired SIO GPIOs so they can be requsted and monitored from power control. Tested: For pass-through, I used gpioset to hold a request on the input GPIOs and confirmed that pass-through remained enabled. For SIO, I used gpioget to confirm that I can successfully request and read the GPIO value. Signed-off-by: Jason M. Bills

Enable pass-through on GPIOE1 and GPIOE3 free

2021-08-02T16:04:00+00:00

This change adds a gpio_disable_free() implementation that checks if the GPIO being freed is GPIOE1 (33) or GPIOE3 (35) and will re-enable the pass-through mux. Tested: Requested GPIOs 33 and 35 and used devmem to check that pass-through was disabled. Then freed them and checked that pass-through was enabled again. Signed-off-by: Jason M. Bills

pinctrl: aspeed: Fix minor documentation error

2021-06-04T12:36:15+00:00

Kernel test robot throws below warning -> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c:2705: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2614: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/pinctrl/aspeed/pinctrl-aspeed.c:111: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/pinctrl/aspeed/pinmux-aspeed.c:24: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst Fix minor documentation error. OpenBMC-Staging-Count: 1 Reported-by: kernel test robot Signed-off-by: Souptick Joarder Cc: Randy Dunlap Reviewed-by: Randy Dunlap Acked-by: Andrew Jeffery Link: https://lore.kernel.org/r/1619353584-8196-1-git-send-email-jrdr.linux@gmail.com Signed-off-by: Linus Walleij Signed-off-by: Joel Stanley

pinctrl: pinctrl-aspeed-g6: Add sgpio pinctrl settings

2021-06-04T12:36:15+00:00

AST2600 supports 2 SGPIO master interfaces and 2 SGPIO slave interfaces. Current pinctrl driver only define the first sgpio master and slave interfaces. The second SGPIO master and slave interfaces should be added in pinctrl driver as well. OpenBMC-Staging-Count: 1 Signed-off-by: Steven Lee Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210525055308.31069-4-steven_lee@aspeedtech.com Signed-off-by: Linus Walleij Signed-off-by: Joel Stanley

pinctrl: aspeed-g5: Adapt to new LPC device tree layout

2021-04-28T07:49:19+00:00

Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei Wang Reviewed-by: Andrew Jeffery Acked-by: Linus Walleij Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20210319062752.145730-4-andrew@aj.id.au Signed-off-by: Joel Stanley (cherry picked from commit eaffd32bea0c93226d4701b1736b04827f754ccf) Signed-off-by: Joel Stanley

pinctrl: aspeed: g6: Fix PWMG0 pinctrl setting

2021-01-27T10:55:05+00:00

[ Upstream commit 92ff62a7bcc17d47c0ce8dddfb7a6e1a2e55ebf4 ] The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from SCU414 to SCU4B4. Signed-off-by: Billy Tsai Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Reviewed-by: Joel Stanley Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20201217024912.3198-1-billy_tsai@aspeedtech.com Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: aspeed: Fix GPIO requests on pass-through banks

2020-12-08T08:23:51+00:00

Commit 6726fbff19bf ("pinctrl: aspeed: Fix GPI only function problem.") fixes access to GPIO banks T and U on the AST2600. Both banks contain input-only pins and the GPIO pin function is named GPITx and GPIUx respectively. Unfortunately the fix had a negative impact on GPIO banks D and E for the AST2400 and AST2500 where the GPIO pass-through functions take similar "GPI"-style names. The net effect on the older SoCs was that when the GPIO subsystem requested a pin in banks D or E be muxed for GPIO, they were instead muxed for pass-through mode. Mistakenly muxing pass-through mode e.g. breaks booting the host on IBM's Witherspoon (AC922) platform where GPIOE0 is used for FSI. Further exploit the names in the provided expression structure to differentiate pass-through from pin-specific GPIO modes. This follow-up fix gives the expected behaviour for the following tests: Witherspoon BMC (AST2500): 1. Power-on the Witherspoon host 2. Request GPIOD1 be muxed via /sys/class/gpio/export 3. Request GPIOE1 be muxed via /sys/class/gpio/export 4. Request the balls for GPIOs E2 and E3 be muxed as GPIO pass-through ("GPIE2" mode) via a pinctrl hog in the devicetree Rainier BMC (AST2600): 5. Request GPIT0 be muxed via /sys/class/gpio/export 6. Request GPIU0 be muxed via /sys/class/gpio/export Together the tests demonstrate that all three pieces of functionality (general GPIOs via 1, 2 and 3, input-only GPIOs via 5 and 6, pass-through mode via 4) operate as desired across old and new SoCs. Fixes: 9b92f5c51e9a ("pinctrl: aspeed: Fix GPI only function problem.") Signed-off-by: Andrew Jeffery Tested-by: Joel Stanley Reviewed-by: Joel Stanley Cc: Billy Tsai Cc: Joel Stanley Link: https://lore.kernel.org/r/20201126063337.489927-1-andrew@aj.id.au Signed-off-by: Linus Walleij