BMC/Intel-BMC/linux.git/drivers/pinctrl/aspeed, branch dev-4.10

pinctrl: aspeed: Rework strap register write logic for the AST2500

2017-12-05T00:34:29+00:00

Yong Li found that writes to the AST2500 strapping register were not properly supported by the Aspeed pinctrl core and provided a patch to rectify the problem. Several revisions of the patch were posted and ultimately v4 should have been applied, however some unfortunate liberal application of tags on my part lead to confusion between v3[1] and v4[2]. Generate the diff between v3 and v4 to apply as a fixup patch. [1] http://patchwork.ozlabs.org/patch/801662/ [2] http://patchwork.ozlabs.org/patch/802946/ Cc: Yong Li Signed-off-by: Andrew Jeffery Signed-off-by: Linus Walleij (cherry picked from commit 5241bd16c7576de3cf189e3e40b01bd4fa10f803) Signed-off-by: Joel Stanley

pinctrl: aspeed: Fix ast2500 strap register write logic

2017-12-05T00:34:25+00:00

On AST2500, the hardware strap register(SCU70) only accepts write ‘1’, to clear it to ‘0’, must set bits(write ‘1’) to SCU7C Signed-off-by: Yong Li Reviewed-by: Andrew Jeffery Tested-by: Andrew Jeffery Signed-off-by: Linus Walleij (cherry picked from commit 1865af212dfa0819ca21c7e5c18c2a75202c1827) Signed-off-by: Joel Stanley

pinctrl: aspeed: Allow disabling Port D and Port E loopback mode

2017-12-05T00:30:52+00:00

Port D and port E GPIO loopback modes are commonly enabled via hardware straps for use with front-panel buttons. When the BMC is powered off or fails to boot, the front-panel buttons are directly connected to the host chipset via the loopback to allow direct power-on and reset control. Once the BMC has booted, the loopback mode must be disabled for the BMC to take over control of host power-on and reset. Disabling these loopback modes requires writing to the hardware strap register which violates the current design of assuming the system designer chose the strap settings for a specific reason and they should be treated as read-only. Only the two bits of the strap register related to these loopback modes are allowed to be written and comments have been added to explain why. Signed-off-by: Rick Altherr Acked-by: Joel Stanley Reviewed-by: Andrew Jeffery Signed-off-by: Linus Walleij (cherry picked from commit c825676b0823fd43a4d08bf865f81bb188b51db1) Signed-off-by: Joel Stanley

pinctrl: aspeed: Fix unused-const-variable warnings

2017-04-27T06:09:58+00:00

Three video input signals suffered from a search/replace failure in some copied code. Signed-off-by: Andrew Jeffery Signed-off-by: Linus Walleij (cherry picked from commit 03ffb507c8c4998fa85d3efae70cb18085457263) Signed-off-by: Joel Stanley

pinctrl: aspeed: g5: Add pinconf support

2017-04-27T05:03:51+00:00

Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery Signed-off-by: Linus Walleij (cherry picked from commit d0639d39fe977608a60e45fb51e25c17661a7ec0) Signed-off-by: Joel Stanley

pinctrl: aspeed: g4: Add pinconf support

2017-04-27T05:03:50+00:00

Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery Signed-off-by: Linus Walleij (cherry picked from commit 47b50b3743cd6a9c2a90372181cfc9ee5b10186d) Signed-off-by: Joel Stanley

pinctrl: aspeed: Add core pinconf support

2017-04-27T05:03:50+00:00

Several pinconf parameters have a fairly straight-forward mapping onto the Aspeed pin controller. These include management of pull-down bias, drive-strength, and some debounce configuration. Pin biasing largely is managed on a per-GPIO-bank basis, aside from the ADC and RMII/RGMII pins. As the bias configuration for each pin in a bank maps onto a single per-bank bit, configuration tables will be introduced to describe the ranges of pins and the supported pinconf parameter. The use of tables also helps with the sparse support of pinconf properties, and the fact that not all GPIO banks support biasing or drive-strength configuration. Further, as the pin controller uses a consistent approach for bias and drive strength configuration at the register level, a second table is defined for looking up the the bit-state required to enable or query the provided configuration. Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto system, and pinctrl-aspeed-g5 on an AST2500EVB as well as under QEMU. The test method was to set the appropriate bits via devmem and verify the result through the controller's pinconf-pins debugfs file. This simultaneously validates the get() path and half of the set() path. The remainder of the set() path was validated by configuring a handful of pins via the devicetree with the supported pinconf properties and verifying the appropriate registers were touched. Signed-off-by: Andrew Jeffery Signed-off-by: Linus Walleij (cherry picked from commit 7f354fd13877aae8abcd7b5a389cc85e3d2e4ed1) Signed-off-by: Joel Stanley

pinctrl: aspeed: g4: Fix mux configuration for GPIOs AA[4-7], AB[0-7]

2017-03-22T13:39:36+00:00

Incorrect video output configuration bits were being tested on pins in GPIO banks AA and AB for the ROM{8,16} mux functions. The ROM{8,16} functions are the highest priority for the relevant pins and also the default function, so we require the relevant video output configuration be disabled to mux GPIO functionality. As the wrong bits were being tested a GPIO export would succeed but leave the pin in an unresponsive state (i.e. value updates were ignored). This misbehaviour was discovered as part of extending the GPIO controller's support to cover banks Y, Z, AA, AB and AC (AC in the case of the g5 SoC). Fixes: 6d329f14a75f ("pinctrl: aspeed-g4: Add mux configuration for all pins") Signed-off-by: Andrew Jeffery Signed-off-by: Linus Walleij (cherry picked from commit 8ccb6dc6e999008bc5d50bdb5badedd636f58e1c) Signed-off-by: Joel Stanley

pinctrl: aspeed: Fix kerneldoc return descriptions

2017-03-22T13:39:36+00:00

Signed-off-by: Andrew Jeffery Acked-by: Joel Stanley Signed-off-by: Linus Walleij (cherry picked from commit b75dd8722e1779767a018009ab6550de33a9136e) Signed-off-by: Joel Stanley

pinctrl: aspeed-g5: Add mux configuration for all pins

2017-03-22T13:39:35+00:00

The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery Acked-by: Joel Stanley Acked-by: Rob Herring Signed-off-by: Linus Walleij (cherry picked from commit f1337856dd88858bf58bd062306ccbfb63303085) Signed-off-by: Joel Stanley