<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/drivers/pci/setup-bus.c, branch dev-5.2</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.2</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.2'/>
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<updated>2019-05-13T23:34:48+00:00</updated>
<entry>
<title>Merge branch 'pci/trivial'</title>
<updated>2019-05-13T23:34:48+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2019-05-13T23:34:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=c7a1c2bbb65e25551d585fba0fd36a01e0a22690'/>
<id>urn:sha1:c7a1c2bbb65e25551d585fba0fd36a01e0a22690</id>
<content type='text'>
  - Cleanup PCI register definitions, typos, etc (Bjorn Helgaas)

  - Remove unnecessary use of user-space types in CPER (Bjorn Helgaas)

  - Cleanup setup-bus.c comments &amp; whitespace (Nicholas Johnson)

* pci/trivial:
  PCI: Cleanup setup-bus.c comments and whitespace
  CPER: Remove unnecessary use of user-space types
  CPER: Add UEFI spec references
  PCI: Fix comment typos
  PCI: Cleanup register definition width and whitespace

# Conflicts:
#	drivers/pci/pci.c
#	drivers/pci/setup-bus.c
</content>
</entry>
<entry>
<title>PCI: Replace dev_printk(KERN_DEBUG) with dev_info(), etc</title>
<updated>2019-05-09T12:49:58+00:00</updated>
<author>
<name>Mohan Kumar</name>
<email>mohankumar718@gmail.com</email>
</author>
<published>2019-04-20T04:07:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=34c6b7105e5a11174f856483cde8ad6e61b7236a'/>
<id>urn:sha1:34c6b7105e5a11174f856483cde8ad6e61b7236a</id>
<content type='text'>
Replace dev_printk(KERN_DEBUG) with dev_info(), etc to be more consistent
with other logging and avoid checkpatch warnings.

The KERN_DEBUG messages could be converted to dev_dbg(), but that depends
on CONFIG_DYNAMIC_DEBUG and DEBUG, and we want most of these messages to
*always* be in the dmesg log.

Link: https://lore.kernel.org/lkml/1555733240-19875-1-git-send-email-mohankumar718@gmail.com
Signed-off-by: Mohan Kumar &lt;mohankumar718@gmail.com&gt;
[bhelgaas: commit log]
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
</content>
</entry>
<entry>
<title>PCI: Cleanup setup-bus.c comments and whitespace</title>
<updated>2019-05-07T20:53:08+00:00</updated>
<author>
<name>Nicholas Johnson</name>
<email>nicholas.johnson-opensource@outlook.com.au</email>
</author>
<published>2019-05-07T19:51:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=0d6076184aecb97cc583bc7f9e125518d6c24404'/>
<id>urn:sha1:0d6076184aecb97cc583bc7f9e125518d6c24404</id>
<content type='text'>
Cleanup comments, kernel-doc, coding style.  No functional changes
intended; comment and whitespace changes only.

Link: https://lore.kernel.org/lkml/PS2P216MB06427E290A68CDB921FB4B2980250@PS2P216MB0642.KORP216.PROD.OUTLOOK.COM
Signed-off-by: Nicholas Johnson &lt;nicholas.johnson-opensource@outlook.com.au&gt;
[bhelgaas: tidy related things throughout the file]
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
</content>
</entry>
<entry>
<title>PCI: Rely on config space header type, not class code</title>
<updated>2019-01-30T16:57:08+00:00</updated>
<author>
<name>Honghui Zhang</name>
<email>honghui.zhang@mediatek.com</email>
</author>
<published>2018-10-16T10:44:43+00:00</published>
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<id>urn:sha1:b2fb5cc574695a32361a6c1878816b3d6563aa0f</id>
<content type='text'>
The PCI configuration space header type tells us whether the device is a
bridge, a CardBus bridge, or a normal device, and defines the layout of the
rest of the header (PCI r3.0 sec 6.1, PCIe r4.0 sec 7.5.1.1.9).

When we rely on the header format, e.g., when we're dealing with bridge
windows, we should check the header type, not the class code.  The class
code is loosely related to the header type, but is often incorrect and the
spec doesn't actually require it to be related to the header format.

Suggested-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Signed-off-by: Honghui Zhang &lt;honghui.zhang@mediatek.com&gt;
[bhelgaas: changelog, keep the PCI_CLASS_BRIDGE_HOST check]
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: Probe bridge window attributes once at enumeration-time</title>
<updated>2019-01-22T18:56:35+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2019-01-19T17:35:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=51c48b310183ab6ba5419edfc6a8de889cc04521'/>
<id>urn:sha1:51c48b310183ab6ba5419edfc6a8de889cc04521</id>
<content type='text'>
pci_bridge_check_ranges() determines whether a bridge supports the optional
I/O and prefetchable memory windows and sets the flag bits in the bridge
resources.  This *could* be done once during enumeration except that the
resource allocation code completely clears the flag bits, e.g., in the
pci_assign_unassigned_bridge_resources() path.

The problem with pci_bridge_check_ranges() in the resource allocation path
is that we may allocate resources after devices have been claimed by
drivers, and pci_bridge_check_ranges() *changes* the window registers to
determine whether they're writable.  This may break concurrent accesses to
devices behind the bridge.

Add a new pci_read_bridge_windows() to determine whether a bridge supports
the optional windows, call it once during enumeration, remember the
results, and change pci_bridge_check_ranges() so it doesn't touch the
bridge windows but sets the flag bits based on those remembered results.

Link: https://lore.kernel.org/linux-pci/1506151482-113560-1-git-send-email-wangzhou1@hisilicon.com
Link: https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg02082.html
Reported-by: Yandong Xu &lt;xuyandong2@huawei.com&gt;
Tested-by: Yandong Xu &lt;xuyandong2@huawei.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Cc: Sagi Grimberg &lt;sagi@grimberg.me&gt;
Cc: Ofer Hayut &lt;ofer@lightbitslabs.com&gt;
Cc: Roy Shterman &lt;roys@lightbitslabs.com&gt;
Cc: Keith Busch &lt;keith.busch@intel.com&gt;
Cc: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;</content>
</entry>
<entry>
<title>PCI: Equalize hotplug memory and io for occupied and empty slots</title>
<updated>2018-10-02T21:04:40+00:00</updated>
<author>
<name>Jon Derrick</name>
<email>jonathan.derrick@intel.com</email>
</author>
<published>2018-09-25T18:39:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=de3ffa301142bf8802a7b0de17f9985acde5c223'/>
<id>urn:sha1:de3ffa301142bf8802a7b0de17f9985acde5c223</id>
<content type='text'>
Currently, a hotplug bridge will be given hpmemsize additional memory
and hpiosize additional io if available, in order to satisfy any future
hotplug allocation requirements.

These calculations don't consider the current memory/io size of the
hotplug bridge/slot, so hotplug bridges/slots which have downstream
devices will be allocated their current allocation in addition to the
hpmemsize value.

This makes for possibly undesirable results with a mix of unoccupied and
occupied slots (ex, with hpmemsize=2M):

  02:03.0 PCI bridge: &lt;-- Occupied
	  Memory behind bridge: d6200000-d64fffff [size=3M]
  02:04.0 PCI bridge: &lt;-- Unoccupied
	  Memory behind bridge: d6500000-d66fffff [size=2M]

This change considers the current allocation size when using the
hpmemsize/hpiosize parameters to make the reservations predictable for
the mix of unoccupied and occupied slots:

  02:03.0 PCI bridge: &lt;-- Occupied
	  Memory behind bridge: d6200000-d63fffff [size=2M]
  02:04.0 PCI bridge: &lt;-- Unoccupied
	  Memory behind bridge: d6400000-d65fffff [size=2M]

Signed-off-by: Jon Derrick &lt;jonathan.derrick@intel.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: Move resource distribution for single bridge outside loop</title>
<updated>2018-06-04T17:08:06+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2018-05-28T12:47:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=14fe5951b667872154d753e451dea043050e9006'/>
<id>urn:sha1:14fe5951b667872154d753e451dea043050e9006</id>
<content type='text'>
If there is only a single bridge on the bus, we assign all resources to it.
Currently this is done as a part of the resource distribution loop but it
does not have to be there, and moving it outside actually improves
readability because we can then save one indent level in the loop.

While there we can add hotplug_bridges == 1 &amp;&amp; normal_bridges == 0 to
the same block because they are dealt the same way.

Suggested-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Reviewed-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;</content>
</entry>
<entry>
<title>PCI: Tidy comments</title>
<updated>2018-03-19T19:20:43+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2018-03-09T22:36:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=df62ab5e0f75608919df7442654b0fab78246b7b'/>
<id>urn:sha1:df62ab5e0f75608919df7442654b0fab78246b7b</id>
<content type='text'>
Remove pointless comments that tell us the file name, remove blank line
comments, follow multi-line comment conventions.  No functional change
intended.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>Merge branch 'pci/spdx' into next</title>
<updated>2018-02-01T17:40:07+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2018-02-01T17:40:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=ab8c609356fbe8dbcd44df11e884ce8cddf3739e'/>
<id>urn:sha1:ab8c609356fbe8dbcd44df11e884ce8cddf3739e</id>
<content type='text'>
* pci/spdx:
  PCI: Add SPDX GPL-2.0+ to replace implicit GPL v2 or later statement
  PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate
  PCI: Add SPDX GPL-2.0 to replace COPYING boilerplate
  PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate
  PCI: Add SPDX GPL-2.0 when no license was specified
</content>
</entry>
<entry>
<title>PCI: Add SPDX GPL-2.0 when no license was specified</title>
<updated>2018-01-26T17:45:16+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2018-01-26T17:45:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=7328c8f48d1895b3fec98b0b319cfb856b4c4fa1'/>
<id>urn:sha1:7328c8f48d1895b3fec98b0b319cfb856b4c4fa1</id>
<content type='text'>
b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
files with no license") added SPDX GPL-2.0 to several PCI files that
previously contained no license information.

Add SPDX GPL-2.0 to all other PCI files that did not contain any license
information and hence were under the default GPL version 2 license of the
kernel.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;</content>
</entry>
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