Intel OpenBMC Linux kernel source tree (mirror) https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.6 2016-03-15T13:56:16+00:00 2016-03-15T13:56:16+00:00 Bjorn Helgaas bhelgaas@google.com 2016-03-15T13:56:16+00:00 urn:sha1:cfeb8139a1fbbbae3f1e986133f4e9e7833eeac4 * pci/host-hv: PCI: hv: Add paravirtual PCI front-end for Microsoft Hyper-V VMs PCI: Look up IRQ domain by fwnode_handle PCI: Add fwnode_handle to x86 pci_sysdata 2016-03-15T13:55:52+00:00 Bjorn Helgaas bhelgaas@google.com 2016-03-15T13:55:52+00:00 urn:sha1:562df5c8521e1371f3cbd0b7b868034da376d714 * pci/host-designware: PCI: designware: Add driver for prototyping kits based on ARC SDP PCI: designware: Add default link up check if sub-driver doesn't override PCI: designware: Add generic dw_pcie_wait_for_link() ARC: Add PCI support 2016-03-15T13:55:19+00:00 Bjorn Helgaas bhelgaas@google.com 2016-03-15T13:55:19+00:00 urn:sha1:c334f9c89e40d2c9f4598e87e186bf3264d39e51 * pci/host-altera: PCI: altera: Fix altera_pcie_link_is_up() * pci/host-imx6: PCI: imx6: Add DT bindings to configure PHY Tx driver settings * pci/host-keystone: PCI: keystone: Defer probing if devm_phy_get() returns -EPROBE_DEFER * pci/host-rcar: PCI: rcar: Depend on ARCH_RENESAS, not ARCH_SHMOBILE * pci/host-tegra: PCI: tegra: Remove misleading PHYS_OFFSET PCI: tegra: Track bus -> CPU mapping PCI: tegra: Remove unused struct tegra_pcie.num_ports field PCI: tegra: Implement ->{add,remove}_bus() callbacks PCI: Add pci_ops.{add,remove}_bus() callbacks * pci/host-thunder: PCI: thunder: Add driver for ThunderX-pass{1,2} on-chip devices PCI: thunder: Add PCIe host driver for ThunderX processors PCI: generic: Expose pci_host_common_probe() for use by other drivers PCI: generic: Add pci_host_common_probe(), based on gen_pci_probe() PCI: generic: Move structure definitions to separate header file * pci/host-vmd: x86/PCI: VMD: Attach VMD resources to parent domain's resource tree x86/PCI: VMD: Set bus resource start to 0 x86/PCI: VMD: Document code for maintainability * pci/host-xilinx: microblaze/PCI: Support generic Xilinx AXI PCIe Host Bridge IP driver PCI: xilinx: Update Zynq binding with Microblaze node PCI: xilinx: Don't call pci_fixup_irqs() on Microblaze PCI: xilinx: Remove dependency on ARM-specific struct hw_pci PCI: xilinx: Use of_pci_get_host_bridge_resources() to parse DT * pci/host-xilinx-nwl: PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller 2016-03-15T13:50:45+00:00 Joao Pinto Joao.Pinto@synopsys.com 2016-03-10T20:44:52+00:00 urn:sha1:5a3aa2a8fae4ce1a3ad786d212b8fffca8ee72f5 Add a reference platform driver for PCI RC IP Protoyping Kits based on the ARC SDP. [bhelgaas: changelog, split patch up, MAINTAINERS update] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> 2016-03-11T22:10:48+00:00 David Daney david.daney@cavium.com 2016-03-04T22:31:48+00:00 urn:sha1:7b6e7ba8e81a862e20d213d90aa5ba1e5a02aba6 The cavium,pci-thunder-ecam devices are exactly ECAM-based PCI root complexes. These root complexes (loosely referred to as ECAM units in the hardware manuals) are used to access the Thunder on-chip devices. They are special in that all the BARs on devices behind these root complexes are at fixed addresses. Add a driver for these devices that synthesizes Enhanced Allocation (EA) capability entries for each BAR. Since this EA synthesis is needed for exactly two chip models, we can hard- code some assumptions about the device topology and the layout of the config space of specific DEVFNs in the driver. [bhelgaas: changelog, whitespace] Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> 2016-03-11T21:53:41+00:00 David Daney david.daney@cavium.com 2016-03-04T22:31:47+00:00 urn:sha1:f12b76e56ada6e276a3d45b60c4e26e2dda7e547 The root complexes used to access off-chip PCIe devices (called PEM units in the hardware manuals) on some Cavium ThunderX processors require quirky access methods for the config space of the PCIe bridge. Add a driver to provide these config space accessor functions. Use the pci-host-common code to configure the PCI machinery. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> 2016-03-11T21:50:20+00:00 David Daney david.daney@cavium.com 2016-03-11T21:35:55+00:00 urn:sha1:4e64dbe226e707b442d45c2096dde2090f34f84d Move pci_host_common_probe() and associated functions to pci-host-common.c, where it can be shared with other drivers. Make it public (not static) and update Kconfig and Makefile to build it. No functional change intended. [bhelgaas: split into separate patch, changelog] Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Will Deacon <will.deacon@arm.com> 2016-03-11T18:42:31+00:00 Bharat Kumar Gogada bharat.kumar.gogada@xilinx.com 2016-03-06T16:32:14+00:00 urn:sha1:ab597d35ef11d2a921e0ec507a9b7861bcb44cbd Add PCIe Root Port driver for Xilinx PCIe NWL bridge IP. [bhelgaas: wait for link like dw_pcie_wait_for_link(), simplify bitmap error path, typos, whitespace, fold in Dan Carpenter's PTR_ERR() fix] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org> 2016-02-16T22:56:12+00:00 Jake Oshins jakeo@microsoft.com 2016-02-16T21:56:23+00:00 urn:sha1:4daace0d8ce851f8f8f91563c835e3000c954d5e Add a new driver which exposes a root PCI bus whenever a PCI Express device is passed through to a guest VM under Hyper-V. The device can be single- or multi-function. The interrupts for the devices are managed by an IRQ domain, implemented within the driver. [bhelgaas: fold in race condition fix (http://lkml.kernel.org/r/1456340196-13717-1-git-send-email-jakeo@microsoft.com)] Signed-off-by: Jake Oshins <jakeo@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> 2016-01-15T18:33:14+00:00 Bjorn Helgaas bhelgaas@google.com 2016-01-15T18:33:14+00:00 urn:sha1:c111e8bf6edfead5602aafa2cda937781737d4f9 * pci/host: PCI: host: Add of_pci_get_host_bridge_resources() stub PCI: host: Mark PCIe/PCI (MSI) IRQ cascade handlers as IRQF_NO_THREAD * pci/host-designware: PCI: designware: Make config accessor override checking symmetric PCI: designware: Simplify control flow * pci/host-hisi: PCI: hisi: Add support for HiSilicon Hip06 PCIe host controllers * pci/host-qcom: ARM: dts: ifc6410: enable PCIe DT node for this board ARM: dts: apq8064: add PCIe devicetree node PCI: qcom: Add Qualcomm PCIe controller driver PCI: qcom: Document PCIe devicetree bindings PCI: designware: Ensure ATU is enabled before IO/conf space accesses * pci/host-rcar: PCI: rcar: Add Gen2 PHY setup to pcie-rcar PCI: rcar: Add runtime PM support to pcie-rcar PCI: rcar: Remove unused pci_sys_data struct from pcie-rcar