<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/drivers/pci/endpoint/functions, branch dev-4.17</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.17</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.17'/>
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<updated>2018-04-03T11:38:05+00:00</updated>
<entry>
<title>PCI: endpoint: Make epc-&gt;ops-&gt;clear_bar()/pci_epc_clear_bar() take struct *epf_bar</title>
<updated>2018-04-03T11:38:05+00:00</updated>
<author>
<name>Niklas Cassel</name>
<email>niklas.cassel@axis.com</email>
</author>
<published>2018-03-28T11:50:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=77d08dbdae2e70a446c61f5db763deed5947acf3'/>
<id>urn:sha1:77d08dbdae2e70a446c61f5db763deed5947acf3</id>
<content type='text'>
Make epc-&gt;ops-&gt;clear_bar()/pci_epc_clear_bar() take struct *epf_bar.

This is needed so that epc-&gt;ops-&gt;clear_bar() can clear the BAR pair,
if the BAR is 64-bits wide.

This also makes it possible for pci_epc_clear_bar() to sanity check
the flags.

Signed-off-by: Niklas Cassel &lt;niklas.cassel@axis.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Gustavo Pimentel &lt;gustavo.pimentel@synopsys.com&gt;
</content>
</entry>
<entry>
<title>PCI: endpoint: Handle 64-bit BARs properly</title>
<updated>2018-04-03T11:38:04+00:00</updated>
<author>
<name>Niklas Cassel</name>
<email>niklas.cassel@axis.com</email>
</author>
<published>2018-03-28T11:50:13+00:00</published>
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<id>urn:sha1:fca83058753456528bef62579ae2b50799d7a473</id>
<content type='text'>
If a 64-bit BAR was set-up, we need to skip a BAR,
since a 64-bit BAR consists of a BAR pair.

We need to check what BAR width the epc-&gt;ops-&gt;set_bar() specific
implementation actually did set-up, since some drivers, like the
Cadence EP controller, sometimes sets up a 64-bit BAR, even though
a 32-bit BAR was requested.

Signed-off-by: Niklas Cassel &lt;niklas.cassel@axis.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Acked-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>PCI: endpoint: Simplify epc-&gt;ops-&gt;set_bar()/pci_epc_set_bar()</title>
<updated>2018-04-03T11:23:38+00:00</updated>
<author>
<name>Niklas Cassel</name>
<email>niklas.cassel@axis.com</email>
</author>
<published>2018-03-28T11:50:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=bc4a48976f57bc88319bfa32690bcc4b6cef4a29'/>
<id>urn:sha1:bc4a48976f57bc88319bfa32690bcc4b6cef4a29</id>
<content type='text'>
Add barno and flags to struct epf_bar.
That way we can simplify epc-&gt;ops-&gt;set_bar()/pci_epc_set_bar()
by passing a struct *epf_bar instead of a whole lot of arguments.

This is needed so that epc-&gt;ops-&gt;set_bar() implementations can
modify BAR flags. Will be utilized in a succeeding patch.

Signed-off-by: Niklas Cassel &lt;niklas.cassel@axis.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Gustavo Pimentel &lt;gustavo.pimentel@synopsys.com&gt;
Acked-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>PCI: endpoint: BAR width should not depend on sizeof dma_addr_t</title>
<updated>2018-04-03T11:23:30+00:00</updated>
<author>
<name>Niklas Cassel</name>
<email>niklas.cassel@axis.com</email>
</author>
<published>2018-03-28T11:50:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=bf597574b6bee5ac741c58da763ad2f10df19065'/>
<id>urn:sha1:bf597574b6bee5ac741c58da763ad2f10df19065</id>
<content type='text'>
If a BAR supports 64-bit width or not depends on the hardware,
and should thus not depend on sizeof(dma_addr_t).

If a certain hardware doesn't support 64-bit BARs, its
epc-&gt;ops-&gt;set_bar() implementation should return -EINVAL
when PCI_BASE_ADDRESS_MEM_TYPE_64 is set.

We can't change pci_epc_set_bar() to only set
PCI_BASE_ADDRESS_MEM_TYPE_64 based on size, since if the user,
for some reason, wants to configure a BAR with a 64-bit width,
even though the BAR size is less than 4 GB, he should be able
to do that.

However, since pci-epf-test is simply a test and not an API,
we can set PCI_BASE_ADDRESS_MEM_TYPE_64 in pci-epf-test itself
only based on size.

Signed-off-by: Niklas Cassel &lt;niklas.cassel@axis.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Acked-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'pci/spdx' into next</title>
<updated>2018-02-01T17:40:07+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2018-02-01T17:40:07+00:00</published>
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<id>urn:sha1:ab8c609356fbe8dbcd44df11e884ce8cddf3739e</id>
<content type='text'>
* pci/spdx:
  PCI: Add SPDX GPL-2.0+ to replace implicit GPL v2 or later statement
  PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate
  PCI: Add SPDX GPL-2.0 to replace COPYING boilerplate
  PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate
  PCI: Add SPDX GPL-2.0 when no license was specified
</content>
</entry>
<entry>
<title>PCI: endpoint: Add the function number as argument to EPC ops</title>
<updated>2018-01-31T11:10:41+00:00</updated>
<author>
<name>Cyrille Pitchen</name>
<email>cyrille.pitchen@free-electrons.com</email>
</author>
<published>2018-01-30T20:56:56+00:00</published>
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<id>urn:sha1:4494738de0d9dc79343fba7c8a57235e684fc549</id>
<content type='text'>
This patch updates the prototype of most handlers from 'struct
pci_epc_ops' so the EPC library can now support multi-function devices.

Signed-off-by: Cyrille Pitchen &lt;cyrille.pitchen@free-electrons.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
</content>
</entry>
<entry>
<title>PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate</title>
<updated>2018-01-28T21:48:29+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2018-01-26T18:50:27+00:00</published>
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<id>urn:sha1:8cfab3cf63cfe5a53e2e566b3b86b30c187edf3a</id>
<content type='text'>
Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license.

Remove the boilerplate GPL version 2 language, relying on the assertion in
b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
files with no license") that the SPDX identifier may be used instead of the
full boilerplate text.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;</content>
</entry>
<entry>
<title>PCI: Add SPDX GPL-2.0 when no license was specified</title>
<updated>2018-01-26T17:45:16+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2018-01-26T17:45:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=7328c8f48d1895b3fec98b0b319cfb856b4c4fa1'/>
<id>urn:sha1:7328c8f48d1895b3fec98b0b319cfb856b4c4fa1</id>
<content type='text'>
b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
files with no license") added SPDX GPL-2.0 to several PCI files that
previously contained no license information.

Add SPDX GPL-2.0 to all other PCI files that did not contain any license
information and hence were under the default GPL version 2 license of the
kernel.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;</content>
</entry>
<entry>
<title>PCI: endpoint: Use correct "end of test" interrupt</title>
<updated>2017-09-20T18:56:06+00:00</updated>
<author>
<name>John Keeping</name>
<email>john@metanate.com</email>
</author>
<published>2017-09-20T18:56:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=749aaf3372b8b56b8743c3e27700d64c8bd06921'/>
<id>urn:sha1:749aaf3372b8b56b8743c3e27700d64c8bd06921</id>
<content type='text'>
pci_epf_test_raise_irq() reads the interrupt to use for the response from
reg-&gt;command, but this has been cleared at the beginning of the command
handler so the value is always zero at this point.

Instead, extract the interrupt index before handling the command and then
pass the requested interrupt into pci_epf_test_raise_irq().  This allows us
to remove the specific code to extract the interrupt for
COMMAND_RAISE_MSI_IRQ since it is now handled in common code.

Fixes: 3ecf3232c54c ("PCI: endpoint: Do not reset *command* inadvertently")
Signed-off-by: John Keeping &lt;john@metanate.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;</content>
</entry>
<entry>
<title>PCI: endpoint: Remove the -&gt;remove() callback</title>
<updated>2017-08-29T21:00:38+00:00</updated>
<author>
<name>Shawn Lin</name>
<email>shawn.lin@rock-chips.com</email>
</author>
<published>2017-08-18T14:58:01+00:00</published>
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<id>urn:sha1:2ca93ffa93122324ce3b0e728d6e80671ea53f17</id>
<content type='text'>
epf_test is allocated using devm_kzalloc(). Hence it's not required to
explicitly free it in remove() callback. Since -&gt;remove() callback doesn't
do anything other than freeing epf_test, remove the -&gt;remove() callback.

Signed-off-by: Shawn Lin &lt;shawn.lin@rock-chips.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
</feed>
