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<title>BMC/Intel-BMC/linux.git/drivers/nvdimm/namespace_devs.c, branch dev-4.3</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.3</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.3'/>
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<updated>2015-08-29T03:40:05+00:00</updated>
<entry>
<title>libnvdimm, pmem: direct map legacy pmem by default</title>
<updated>2015-08-29T03:40:05+00:00</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2015-08-24T23:20:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=004f1afbe199e6ab20805b95aefd83ccd24bc5c7'/>
<id>urn:sha1:004f1afbe199e6ab20805b95aefd83ccd24bc5c7</id>
<content type='text'>
The expectation is that the legacy / non-standard pmem discovery method
(e820 type-12) will only ever be used to describe small quantities of
persistent memory.  Larger capacities will be described via the ACPI
NFIT.  When "allocate struct page from pmem" support is added this default
policy can be overridden by assigning a legacy pmem namespace to a pfn
device, however this would be only be necessary if a platform used the
legacy mechanism to define a very large range.

Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm, pfn: 'struct page' provider infrastructure</title>
<updated>2015-08-29T03:39:36+00:00</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2015-07-30T21:57:47+00:00</published>
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<id>urn:sha1:e1455744b27c9e6115c3508a7b2902157c2c4347</id>
<content type='text'>
Implement the base infrastructure for libnvdimm PFN devices. Similar to
BTT devices they take a namespace as a backing device and layer
functionality on top. In this case the functionality is reserving space
for an array of 'struct page' entries to be handed out through
pfn_to_page(). For now this is just the basic libnvdimm-device-model for
configuring the base PFN device.

As the namespace claiming mechanism for PFN devices is mostly identical
to BTT devices drivers/nvdimm/claim.c is created to house the common
bits.

Cc: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm, btt: write and validate parent_uuid</title>
<updated>2015-08-14T17:43:04+00:00</updated>
<author>
<name>Vishal Verma</name>
<email>vishal.l.verma@intel.com</email>
</author>
<published>2015-07-29T20:58:09+00:00</published>
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<id>urn:sha1:6ec689542b5bc516187917d49b112847dfb75b0b</id>
<content type='text'>
When a BTT is instantiated on a namespace it must validate the namespace
uuid matches the 'parent_uuid' stored in the btt superblock. This
property enforces that changing the namespace UUID invalidates all
former BTT instances on that storage. For "IO namespaces" that don't
have a label or UUID, the parent_uuid is set to zero, and this
validation is skipped. For such cases, old BTTs have to be invalidated
by forcing the namespace to raw mode, and overwriting the BTT info
blocks.

Based on a patch by Dan Williams &lt;dan.j.williams@intel.com&gt;

Signed-off-by: Vishal Verma &lt;vishal.l.verma@intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm: Add sysfs numa_node to NVDIMM devices</title>
<updated>2015-06-26T15:23:38+00:00</updated>
<author>
<name>Toshi Kani</name>
<email>toshi.kani@hp.com</email>
</author>
<published>2015-06-19T18:18:34+00:00</published>
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<id>urn:sha1:74ae66c3b14ffa94c8d2dea201cdf8e6203d13d5</id>
<content type='text'>
Add support of sysfs 'numa_node' to I/O-related NVDIMM devices
under /sys/bus/nd/devices, regionN, namespaceN.0, and bttN.x.

An example of numa_node values on a 2-socket system with a single
NVDIMM range on each socket is shown below.
  /sys/bus/nd/devices
  |-- btt0.0/numa_node:0
  |-- btt1.0/numa_node:1
  |-- btt1.1/numa_node:1
  |-- namespace0.0/numa_node:0
  |-- namespace1.0/numa_node:1
  |-- region0/numa_node:0
  |-- region1/numa_node:1

These numa_node files are then linked under the block class of
their device names.
  /sys/class/block/pmem0/device/numa_node:0
  /sys/class/block/pmem1s/device/numa_node:1

This enables numactl(8) to accept 'block:' and 'file:' paths of
pmem and btt devices as shown in the examples below.
  numactl --preferred block:pmem0 --show
  numactl --preferred file:/dev/pmem1s --show

Signed-off-by: Toshi Kani &lt;toshi.kani@hp.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm, blk: add support for blk integrity</title>
<updated>2015-06-26T15:23:38+00:00</updated>
<author>
<name>Vishal Verma</name>
<email>vishal.l.verma@intel.com</email>
</author>
<published>2015-06-25T08:22:39+00:00</published>
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<id>urn:sha1:fcae695737fca0849c18db814d9d8de05c0fd2a2</id>
<content type='text'>
Support multiple block sizes (sector + metadata) for nd_blk in the
same way as done for the BTT. Add the idea of an 'internal' lbasize,
which is properly aligned and padded, and store metadata in this space.

Signed-off-by: Vishal Verma &lt;vishal.l.verma@linux.intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;</content>
</entry>
<entry>
<title>libnvdimm, nfit, nd_blk: driver for BLK-mode access persistent memory</title>
<updated>2015-06-26T15:23:38+00:00</updated>
<author>
<name>Ross Zwisler</name>
<email>ross.zwisler@linux.intel.com</email>
</author>
<published>2015-06-25T08:21:02+00:00</published>
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<id>urn:sha1:047fc8a1f9a6330eacc80374dff087e20dc2304b</id>
<content type='text'>
The libnvdimm implementation handles allocating dimm address space (DPA)
between PMEM and BLK mode interfaces.  After DPA has been allocated from
a BLK-region to a BLK-namespace the nd_blk driver attaches to handle I/O
as a struct bio based block device. Unlike PMEM, BLK is required to
handle platform specific details like mmio register formats and memory
controller interleave.  For this reason the libnvdimm generic nd_blk
driver calls back into the bus provider to carry out the I/O.

This initial implementation handles the BLK interface defined by the
ACPI 6 NFIT [1] and the NVDIMM DSM Interface Example [2] composed from
DCR (dimm control region), BDW (block data window), IDT (interleave
descriptor) NFIT structures and the hardware register format.
[1]: http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf
[2]: http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf

Cc: Andy Lutomirski &lt;luto@amacapital.net&gt;
Cc: Boaz Harrosh &lt;boaz@plexistor.com&gt;
Cc: H. Peter Anvin &lt;hpa@zytor.com&gt;
Cc: Jens Axboe &lt;axboe@fb.com&gt;
Cc: Ingo Molnar &lt;mingo@kernel.org&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
Acked-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;</content>
</entry>
<entry>
<title>nd_btt: atomic sector updates</title>
<updated>2015-06-26T15:23:38+00:00</updated>
<author>
<name>Vishal Verma</name>
<email>vishal.l.verma@intel.com</email>
</author>
<published>2015-06-25T08:20:32+00:00</published>
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<id>urn:sha1:5212e11fde4d40fa627668b4f2222d20db488f71</id>
<content type='text'>
BTT stands for Block Translation Table, and is a way to provide power
fail sector atomicity semantics for block devices that have the ability
to perform byte granularity IO. It relies on the capability of libnvdimm
namespace devices to do byte aligned IO.

The BTT works as a stacked blocked device, and reserves a chunk of space
from the backing device for its accounting metadata. It is a bio-based
driver because all IO is done synchronously, and there is no queuing or
asynchronous completions at either the device or the driver level.

The BTT uses 'lanes' to index into various 'on-disk' data structures,
and lanes also act as a synchronization mechanism in case there are more
CPUs than available lanes. We did a comparison between two lane lock
strategies - first where we kept an atomic counter around that tracked
which was the last lane that was used, and 'our' lane was determined by
atomically incrementing that. That way, for the nr_cpus &gt; nr_lanes case,
theoretically, no CPU would be blocked waiting for a lane. The other
strategy was to use the cpu number we're scheduled on to and hash it to
a lane number. Theoretically, this could block an IO that could've
otherwise run using a different, free lane. But some fio workloads
showed that the direct cpu -&gt; lane hash performed faster than tracking
'last lane' - my reasoning is the cache thrash caused by moving the
atomic variable made that approach slower than simply waiting out the
in-progress IO. This supports the conclusion that the driver can be a
very simple bio-based one that does synchronous IOs instead of queuing.

Cc: Andy Lutomirski &lt;luto@amacapital.net&gt;
Cc: Boaz Harrosh &lt;boaz@plexistor.com&gt;
Cc: H. Peter Anvin &lt;hpa@zytor.com&gt;
Cc: Jens Axboe &lt;axboe@fb.com&gt;
Cc: Ingo Molnar &lt;mingo@kernel.org&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Neil Brown &lt;neilb@suse.de&gt;
Cc: Jeff Moyer &lt;jmoyer@redhat.com&gt;
Cc: Dave Chinner &lt;david@fromorbit.com&gt;
Cc: Greg KH &lt;gregkh@linuxfoundation.org&gt;
[jmoyer: fix nmi watchdog timeout in btt_map_init]
[jmoyer: move btt initialization to module load path]
[jmoyer: fix memory leak in the btt initialization path]
[jmoyer: Don't overwrite corrupted arenas]
Signed-off-by: Vishal Verma &lt;vishal.l.verma@linux.intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;</content>
</entry>
<entry>
<title>libnvdimm: infrastructure for btt devices</title>
<updated>2015-06-25T08:20:04+00:00</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2015-06-25T08:20:04+00:00</published>
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<id>urn:sha1:8c2f7e8658df1d3b7cbfa62706941d14c715823a</id>
<content type='text'>
NVDIMM namespaces, in addition to accepting "struct bio" based requests,
also have the capability to perform byte-aligned accesses.  By default
only the bio/block interface is used.  However, if another driver can
make effective use of the byte-aligned capability it can claim namespace
interface and use the byte-aligned -&gt;rw_bytes() interface.

The BTT driver is the initial first consumer of this mechanism to allow
adding atomic sector update semantics to a pmem or blk namespace.  This
patch is the sysfs infrastructure to allow configuring a BTT instance
for a namespace.  Enabling that BTT and performing i/o is in a
subsequent patch.

Cc: Greg KH &lt;gregkh@linuxfoundation.org&gt;
Cc: Neil Brown &lt;neilb@suse.de&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;</content>
</entry>
<entry>
<title>libnvdimm: write blk label set</title>
<updated>2015-06-25T01:24:10+00:00</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2015-05-30T16:35:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=0ba1c634892b3590779803a701bcb82e8c32cc7a'/>
<id>urn:sha1:0ba1c634892b3590779803a701bcb82e8c32cc7a</id>
<content type='text'>
After 'uuid', 'size', 'sector_size', and optionally 'alt_name' have been
set to valid values the labels on the dimm can be updated.  The
difference with the pmem case is that blk namespaces are limited to one
dimm and can cover discontiguous ranges in dpa space.

Also, after allocating label slots, it is useful for userspace to know
how many slots are left.  Export this information in sysfs.

Cc: Greg KH &lt;gregkh@linuxfoundation.org&gt;
Cc: Neil Brown &lt;neilb@suse.de&gt;
Acked-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm: write pmem label set</title>
<updated>2015-06-25T01:24:10+00:00</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2015-05-30T16:36:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=f524bf271a5cf12a44253194abcf8b6688ff5b9d'/>
<id>urn:sha1:f524bf271a5cf12a44253194abcf8b6688ff5b9d</id>
<content type='text'>
After 'uuid', 'size', and optionally 'alt_name' have been set to valid
values the labels on the dimms can be updated.

Write procedure is:
1/ Allocate and write new labels in the "next" index
2/ Free the old labels in the working copy
3/ Write the bitmap and the label space on the dimm
4/ Write the index to make the update valid

Label ranges directly mirror the dpa resource values for the given
label_id of the namespace.

Cc: Greg KH &lt;gregkh@linuxfoundation.org&gt;
Cc: Neil Brown &lt;neilb@suse.de&gt;
Acked-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
</feed>
