<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/drivers/ntb/hw/amd, branch dev-4.6</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.6</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.6'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2016-03-26T15:44:33+00:00</updated>
<entry>
<title>NTB: Remove _addr functions from ntb_hw_amd</title>
<updated>2016-03-26T15:44:33+00:00</updated>
<author>
<name>Allen Hubbe</name>
<email>Allen.Hubbe@emc.com</email>
</author>
<published>2016-03-21T08:53:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=4f1b50c3e3082b31c94cee2b897bd9f5d0f3e7c8'/>
<id>urn:sha1:4f1b50c3e3082b31c94cee2b897bd9f5d0f3e7c8</id>
<content type='text'>
Kernel zero day testing warned about address space confusion.  A virtual
iomem address was used where a physical address is expected.  The
offending functions implement an optional part of the api, so they are
removed.  They can be added later, after testing.

Fixes: a1b3695820aa490e58915d720a1438069813008b

Signed-off-by: Allen Hubbe &lt;Allen.Hubbe@emc.com&gt;
Acked-by: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
</entry>
<entry>
<title>NTB: Add support for AMD PCI-Express Non-Transparent Bridge</title>
<updated>2016-01-22T00:51:04+00:00</updated>
<author>
<name>Xiangliang Yu</name>
<email>Xiangliang.Yu@amd.com</email>
</author>
<published>2016-01-21T11:47:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=a1b3695820aa490e58915d720a1438069813008b'/>
<id>urn:sha1:a1b3695820aa490e58915d720a1438069813008b</id>
<content type='text'>
This adds support for AMD's PCI-Express Non-Transparent Bridge
(NTB) device on the Zeppelin platform. The driver connnects to the
standard NTB sub-system interface, with modification to add hooks
for power management in a separate patch. The AMD NTB device has 3
memory windows, 16 doorbell, 16 scratch-pad registers, and supports
up to 16 PCIe lanes running a Gen3 speeds.

Signed-off-by: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Reviewed-by: Allen Hubbe &lt;Allen.Hubbe@emc.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
</entry>
</feed>
