BMC/Intel-BMC/linux.git/drivers/net/phy/realtek.c, branch dev-5.2

net: phy: realtek: Replace phy functions with non-locked version in rtl8211e_config_init()

2019-05-13T16:10:39+00:00

After calling phy_select_page() and until calling phy_restore_page(), the mutex 'mdio_lock' is already locked, so the driver should use non-locked version of phy functions. Or there will be a deadlock with 'mdio_lock'. This replaces phy functions called from rtl8211e_config_init() to avoid the deadlock issue. Fixes: f81dadbcf7fd ("net: phy: realtek: Add rtl8211e rx/tx delays config") Signed-off-by: Kunihiko Hayashi Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller

net: phy: realtek: fix double page ops in generic Realtek driver

2019-05-11T17:00:20+00:00

When adding missing callbacks I missed that one had them set already. Interesting that the compiler didn't complain. Fixes: daf3ddbe11a2 ("net: phy: realtek: add missing page operations") Signed-off-by: Heiner Kallweit Signed-off-by: David S. Miller

net: phy: realtek: add missing page operations

2019-05-10T22:20:59+00:00

Add missing page operation callbacks to few Realtek drivers. This also fixes a NPE after the referenced commit added code to the RTL8211E driver that uses phy_select_page(). Fixes: f81dadbcf7fd ("net: phy: realtek: Add rtl8211e rx/tx delays config") Signed-off-by: Heiner Kallweit Reviewed-by: Florian Fainelli Reported-by: Vicente Bergas Signed-off-by: David S. Miller

net: phy: realtek: Change TX-delay setting for RGMII modes only

2019-05-08T23:31:38+00:00

It's prone to problems if delay is cleared out for other than RGMII modes. So lets set/clear the TX-delay in the config register only if actually RGMII-like interface mode is requested. This only concerns rtl8211f chips. Signed-off-by: Serge Semin Signed-off-by: David S. Miller

net: phy: realtek: Add rtl8211e rx/tx delays config

2019-05-08T23:31:38+00:00

There are two chip pins named TXDLY and RXDLY which actually adds the 2ns delays to TXC and RXC for TXD/RXD latching. Alas this is the only documented info regarding the RGMII timing control configurations the PHY provides. It turns out the same settings can be setup via MDIO registers hidden in the extension pages layout. Particularly the extension page 0xa4 provides a register 0x1c, which bits 1 and 2 control the described delays. They are used to implement the "rgmii-{id,rxid,txid}" phy-mode. The hidden RGMII configs register utilization was found in the rtl8211e U-boot driver: https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99 There is also a freebsd-folks discussion regarding this register: https://reviews.freebsd.org/D13591 It confirms that the register bits field must control the so called configuration pins described in the table 12-13 of the official PHY datasheet: 8:6 = PHY Address 5:4 = Auto-Negotiation 3 = Interface Mode Select 2 = RX Delay 1 = TX Delay 0 = SELRGV Reviewed-by: Andrew Lunn Signed-off-by: Serge Semin Signed-off-by: David S. Miller

net: phy: realtek: remove setting callback get_features and use phylib fallback

2019-04-05T00:55:37+00:00

Now that phylib uses genphy_read_abilities() as fallback, we don't have to set callback get_features any longer. Signed-off-by: Heiner Kallweit Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller

net: phy: realtek: use genphy_read_abilities

2019-04-02T20:09:56+00:00

Use new function genphy_read_abilities(). This allows to remove all calls to genphy_config_init(). Signed-off-by: Heiner Kallweit Signed-off-by: David S. Miller

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

2019-02-24T20:06:19+00:00

Three conflicts, one of which, for marvell10g.c is non-trivial and requires some follow-up from Heiner or someone else. The issue is that Heiner converted the marvell10g driver over to use the generic c45 code as much as possible. However, in 'net' a bug fix appeared which makes sure that a new local mask (MDIO_AN_10GBT_CTRL_ADV_NBT_MASK) with value 0x01e0 is cleared. Signed-off-by: David S. Miller

net: phy: realtek: Dummy IRQ calls for RTL8366RB

2019-02-24T02:45:28+00:00

This fixes a regression introduced by commit 0d2e778e38e0ddffab4bb2b0e9ed2ad5165c4bf7 "net: phy: replace PHY_HAS_INTERRUPT with a check for config_intr and ack_interrupt". This assumes that a PHY cannot trigger interrupt unless it has .config_intr() or .ack_interrupt() implemented. A later patch makes the code assume both need to be implemented for interrupts to be present. But this PHY (which is inside a DSA) will happily fire interrupts without either callback. Implement dummy callbacks for .config_intr() and .ack_interrupt() in the phy header to fix this. Tested on the RTL8366RB on D-Link DIR-685. Fixes: 0d2e778e38e0 ("net: phy: replace PHY_HAS_INTERRUPT with a check for config_intr and ack_interrupt") Cc: Heiner Kallweit Signed-off-by: Linus Walleij Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller

net: phy: realtek: add generic Realtek PHY driver

2019-02-03T17:37:08+00:00

The integrated PHY's of later RTL8168 network chips report the generic PHYID 0x001cc800 (Realtek OUI, model and revision number both set to zero) and therefore currently the genphy driver is used. To be able to use the paged version of e.g. phy_write() we need a PHY driver with the read_page and write_page callbacks implemented. So basically make a copy of the genphy driver, just with the read_page and write_page callbacks being set. Signed-off-by: Heiner Kallweit Signed-off-by: David S. Miller