BMC/Intel-BMC/linux.git/drivers/mtd, branch dev-5.2

Merge tag 'v5.2.7' into dev-5.2

2019-08-09T07:15:09+00:00

This is the 5.2.7 stable release Signed-off-by: Joel Stanley

mtd: rawnand: micron: handle on-die "ECC-off" devices correctly

2019-08-06T17:08:16+00:00

commit 8493b2a06fc5b77ef5c579dc32b12761f7b7a84c upstream. Some devices are not supposed to support on-die ECC but experience shows that internal ECC machinery can actually be enabled through the "SET FEATURE (EFh)" command, even if a read of the "READ ID Parameter Tables" returns that it is not. Currently, the driver checks the "READ ID Parameter" field directly after having enabled the feature. If the check fails it returns immediately but leaves the ECC on. When using buggy chips like MT29F2G08ABAGA and MT29F2G08ABBGA, all future read/program cycles will go through the on-die ECC, confusing the host controller which is supposed to be the one handling correction. To address this in a common way we need to turn off the on-die ECC directly after reading the "READ ID Parameter" and before checking the "ECC status". Cc: stable@vger.kernel.org Fixes: dbc44edbf833 ("mtd: rawnand: micron: Fix on-die ECC detection logic") Signed-off-by: Marco Felsch Reviewed-by: Boris Brezillon Signed-off-by: Miquel Raynal Signed-off-by: Greg Kroah-Hartman

mtd: spinand: read returns badly if the last page has bitflips

2019-07-26T07:11:09+00:00

commit b83408b580eccf8d2797cd6cb9ae42c2a28656a7 upstream. In case of the last page containing bitflips (ret > 0), spinand_mtd_read() will return that number of bitflips for the last page while it should instead return max_bitflips like it does when the last page read returns with 0. Signed-off-by: Weixiong Liao Reviewed-by: Boris Brezillon Reviewed-by: Frieder Schrempf Cc: stable@vger.kernel.org Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: Miquel Raynal Signed-off-by: Greg Kroah-Hartman

mtd: rawnand: mtk: Correct low level time calculation of r/w cycle

2019-07-26T07:11:09+00:00

commit e1884ffddacc0424d7e785e6f8087bd12f7196db upstream. At present, the flow of calculating AC timing of read/write cycle in SDR mode is that: At first, calculate high hold time which is valid for both read and write cycle using the max value between tREH_min and tWH_min. Secondly, calculate WE# pulse width using tWP_min. Thridly, calculate RE# pulse width using the bigger one between tREA_max and tRP_min. But NAND SPEC shows that Controller should also meet write/read cycle time. That is write cycle time should be more than tWC_min and read cycle should be more than tRC_min. Obviously, we do not achieve that now. This patch corrects the low level time calculation to meet minimum read/write cycle time required. After getting the high hold time, WE# low level time will be promised to meet tWP_min and tWC_min requirement, and RE# low level time will be promised to meet tREA_max, tRP_min and tRC_min requirement. Fixes: edfee3619c49 ("mtd: nand: mtk: add ->setup_data_interface() hook") Cc: stable@vger.kernel.org # v4.17+ Signed-off-by: Xiaolei Li Reviewed-by: Miquel Raynal Signed-off-by: Miquel Raynal Signed-off-by: Greg Kroah-Hartman

mtd: spi-nor: aspeed: add support for the 4B opcodes

2019-07-10T07:30:15+00:00

Switch the default controller value to use the read mode in order to customize the command and use SPINOR_OP_READ_4B (0x13) when the chip supports 4B opcodes. OpenBMC-Staging-Count: 3 Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery

mtd: spi-nor: aspeed: use memcpy_fromio() to capture the optimization buffer

2019-07-10T07:30:15+00:00

aspeed_smc_read_from_ahb() only reads the first word which is not what we want. We want to capture a CALIBRATE_BUF_SIZE size window of the flash contents to optimize the read. OpenBMC-Staging-Count: 3 Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery

mtd: spi-nor: aspeed: clarify 4BYTE address mode mask

2019-07-10T07:30:15+00:00

OpenBMC-Staging-Count: 3 Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery

mtd: spi-nor: aspeed: introduce a aspeed_smc_default_read() helper

2019-07-10T07:30:15+00:00

OpenBMC-Staging-Count: 3 Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery

mtd: spi-nor: add NPCM FIU controller driver

2019-07-10T07:09:14+00:00

Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI-NOR controller driver The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon [v5.0: Remove asm/size.h include to fix build] Signed-off-by: Joel Stanley

mtd: spi-nor: fix options for mx66l51235f

2019-07-10T07:09:13+00:00

Currently in driver spi-nor there is a line for mx66l51235l. According to Macronix site there is no such part number. The chip detected as such is actually mx66l51235f. According to the datasheet for mx66l51235f, "The device default is in 24-bit address mode" (section 9-10). Hence we removed SPI_NOR_4B_OPCODES option with this commit. OpenBMC-Staging-Count: 6 Fixes: d342b6a973af ("mtd: spi-nor: enable 4B opcodes for mx66l51235l") Signed-off-by: Alexander Soldatov Reviewed-by: Cédric Le Goater Reviewed-by: Lei YU Signed-off-by: Joel Stanley