BMC/Intel-BMC/linux.git/drivers/mtd, branch dev-5.1

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-07-02T05:03:44+00:00

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman (cherry picked from commit 2874c5fd284268364ece81a7bd936f3c8168e567) Signed-off-by: Joel Stanley

Merge tag 'v5.1.5' into dev-5.1

2019-05-27T04:07:53+00:00

This is the 5.1.5 stable release Signed-off-by: Joel Stanley

mtd: maps: Allow MTD_PHYSMAP with MTD_RAM

2019-05-22T05:39:52+00:00

commit d41970097f10d898cef0eb04bf53d786efd6bbbc upstream. When the physmap_of_core.c code was merged into physmap-core.c the ability to use MTD_PHYSMAP_OF with only MTD_RAM selected was lost. Restore this by adding MTD_RAM to the dependencies of MTD_PHYSMAP. Fixes: commit 642b1e8dbed7 ("mtd: maps: Merge physmap_of.c into physmap-core.c") Cc: Signed-off-by: Chris Packham Reviewed-by: Hamish Martin Signed-off-by: Richard Weinberger Signed-off-by: Greg Kroah-Hartman

mtd: maps: physmap: Store gpio_values correctly

2019-05-22T05:39:52+00:00

commit 64d14c6fe040361ff6aecb825e392cf97837cd9e upstream. When the gpio-addr-flash.c driver was merged with physmap-core.c the code to store the current gpio_values was lost. This meant that once a gpio was asserted it was never de-asserted. Fix this by storing the current offset in gpio_values like the old driver used to. Fixes: commit ba32ce95cbd9 ("mtd: maps: Merge gpio-addr-flash.c into physmap-core.c") Cc: Signed-off-by: Chris Packham Reviewed-by: Boris Brezillon Signed-off-by: Richard Weinberger Signed-off-by: Greg Kroah-Hartman

mtd: spi-nor: intel-spi: Avoid crossing 4K address boundary on read/write

2019-05-22T05:39:52+00:00

commit 2b75ebeea6f4937d4d05ec4982c471cef9a29b7f upstream. It was observed that reads crossing 4K address boundary are failing. This limitation is mentioned in Intel documents: Intel(R) 9 Series Chipset Family Platform Controller Hub (PCH) Datasheet: "5.26.3 Flash Access Program Register Access: * Program Register Accesses are not allowed to cross a 4 KB boundary..." Enhanced Serial Peripheral Interface (eSPI) Interface Base Specification (for Client and Server Platforms): "5.1.4 Address For other memory transactions, the address may start or end at any byte boundary. However, the address and payload length combination must not cross the naturally aligned address boundary of the corresponding Maximum Payload Size. It must not cross a 4 KB address boundary." Avoid this by splitting an operation crossing the boundary into two operations. Fixes: 8afda8b26d01 ("spi-nor: Add support for Intel SPI serial flash controller") Cc: stable@vger.kernel.org Reported-by: Romain Porte Tested-by: Pascal Fabreges Signed-off-by: Alexander Sverdlin Reviewed-by: Tudor Ambarus Acked-by: Mika Westerberg Signed-off-by: Miquel Raynal Signed-off-by: Greg Kroah-Hartman

mtd: spi-nor: aspeed: add support for the 4B opcodes

2019-05-07T07:34:44+00:00

Switch the default controller value to use the read mode in order to customize the command and use SPINOR_OP_READ_4B (0x13) when the chip supports 4B opcodes. OpenBMC-Staging-Count: 2 Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery

mtd: spi-nor: aspeed: use memcpy_fromio() to capture the optimization buffer

2019-05-07T07:34:44+00:00

aspeed_smc_read_from_ahb() only reads the first word which is not what we want. We want to capture a CALIBRATE_BUF_SIZE size window of the flash contents to optimize the read. OpenBMC-Staging-Count: 2 Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery

mtd: spi-nor: aspeed: clarify 4BYTE address mode mask

2019-05-07T07:34:44+00:00

OpenBMC-Staging-Count: 2 Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery

mtd: spi-nor: aspeed: introduce a aspeed_smc_default_read() helper

2019-05-07T07:34:44+00:00

OpenBMC-Staging-Count: 2 Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery

mtd: spi-nor: add NPCM FIU controller driver

2019-05-06T04:13:02+00:00

Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI-NOR controller driver The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. OpenBMC-Staging-Count: 3 Signed-off-by: Tomer Maimon [v5.0: Remove asm/size.h include to fix build] Signed-off-by: Joel Stanley