<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/drivers/mmc/core/sd.c, branch dev-4.17</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.17</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.17'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2018-03-15T13:43:05+00:00</updated>
<entry>
<title>mmc: core: Export card RCA register via sysfs</title>
<updated>2018-03-15T13:43:05+00:00</updated>
<author>
<name>Harish Jenny K N</name>
<email>harish_kandiga@mentor.com</email>
</author>
<published>2018-03-07T05:01:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=974e85e90c84a32f49b70c6615f1e8f156f38a3c'/>
<id>urn:sha1:974e85e90c84a32f49b70c6615f1e8f156f38a3c</id>
<content type='text'>
This patch exports RCA register to sysfs which will help in reading the
disk identification information.

Reviewed-by: Shawn Lin &lt;shawn.lin@rock-chips.com&gt;
Signed-off-by: Harish Jenny K N &lt;harish_kandiga@mentor.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: sd: Remove redundant err assignment from mmc_read_switch</title>
<updated>2018-03-15T08:32:30+00:00</updated>
<author>
<name>Shawn Lin</name>
<email>shawn.lin@rock-chips.com</email>
</author>
<published>2018-02-27T01:26:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=3715ce57f4d26d09fc1813d157286abc5aa319a5'/>
<id>urn:sha1:3715ce57f4d26d09fc1813d157286abc5aa319a5</id>
<content type='text'>
Variable err would be firstly initialized by the return value of
mmc_sd_switch().

Signed-off-by: Shawn Lin &lt;shawn.lin@rock-chips.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: core: Don't try UHS-I mode if 4-bit mode isn't supported</title>
<updated>2018-03-15T08:30:39+00:00</updated>
<author>
<name>Shawn Lin</name>
<email>shawn.lin@rock-chips.com</email>
</author>
<published>2018-02-27T00:49:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=d6743a8a1ae38269a41094ad14d7ef86199f661d'/>
<id>urn:sha1:d6743a8a1ae38269a41094ad14d7ef86199f661d</id>
<content type='text'>
Per SD specification physical layer v4.0, section 3.9.4, it
says "UHS-I supports only 4-bit mode. Host shall select 4-bit
mode by ACMD6. However mmc_sd_init_uhs_card() still go ahead
to initialize the cards anyway, whether card or host won't
support 4-bit mode.

  This breaks the platforms which could support UHS-I mode but on
some certain boards only support 1-bit mode with a UHS-I card inserted,
as all the tuning process is broken due to this. Alternatively, we
should check the return value from mmc_set_bus_width() to see if host
could finish the request to switch the bus width on its side. But that
needs more thing to do than this patch that just bails out early to try
high speed mode if 4-bit mode isn't available for whatever reason. And
this patch could also fix the same problem for sdio since R4_18V_PRESENT
won't be set for ocr when mmc_sdio_init_card() finds mmc_host_uhs()
is false.

  Note that this patch doesn't keep the checking of card-&gt;scr.sda_spec3
and comparing card-&gt;scr.bus_widths with SD_SCR_BUS_WIDTH_4 within
mmc_sd_init_uhs_card() since if the sd cards response with SD_ROCR_S18A,
it definitely supports UHS-I mode, which implicitly means these checkings
are always true.

Signed-off-by: Shawn Lin &lt;shawn.lin@rock-chips.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: core: prepend 0x to OCR entry in sysfs</title>
<updated>2017-11-29T09:46:53+00:00</updated>
<author>
<name>Bastian Stender</name>
<email>bst@pengutronix.de</email>
</author>
<published>2017-11-28T08:24:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=c892b0d81705c566f575e489efc3c50762db1bde'/>
<id>urn:sha1:c892b0d81705c566f575e489efc3c50762db1bde</id>
<content type='text'>
The sysfs entry "ocr" was missing the 0x prefix to identify it as hex
formatted.

Fixes: 5fb06af7a33b ("mmc: core: Extend sysfs with OCR register")
Signed-off-by: Bastian Stender &lt;bst@pengutronix.de&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v4.8+
[Ulf: Amended change to also cover SD-cards]
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: sd: Fix signal voltage when there is no power cycle</title>
<updated>2017-10-30T10:45:57+00:00</updated>
<author>
<name>Adrian Hunter</name>
<email>adrian.hunter@intel.com</email>
</author>
<published>2017-09-25T08:29:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=6a11fc47f175c8d87018e89cb58e2d36c66534cb'/>
<id>urn:sha1:6a11fc47f175c8d87018e89cb58e2d36c66534cb</id>
<content type='text'>
Some boards have SD card connectors where the power rail cannot be switched
off by the driver. However there are various circumstances when a card
might be re-initialized, such as after system resume, warm re-boot, or
error handling. However, a UHS card will continue to use 1.8V signaling
unless it is power cycled.

If the card has not been power cycled, it may still be using 1.8V
signaling. According to the SD spec., the Bus Speed Mode (function group 1)
bits 2 to 4 are zero if the card is initialized at 3.3V signal level. Thus
they can be used to determine if the card has already switched to 1.8V
signaling. Detect that situation and try to initialize a UHS-I (1.8V)
transfer mode.

Tested with the following cards:
  Transcend 4GB High Speed
  Kingston 64GB SDR104
  Lexar by Micron HIGH-PERFORMANCE 300x 16GB DDR50
  SanDisk Ultra 8GB DDR50
  Transcend Ultimate 600x 16GB SDR104
  Transcend Premium 300x 64GB SDR104
  Lexar by Micron Professional 1000x 32GB UHS-II SDR104
  SanDisk Extreme Pro 16GB SDR104

Signed-off-by: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Tested-by: Zhoujie Wu &lt;zjwu@marvell.com&gt;
Reviewed-by: Shawn Lin &lt;shawn.lin@rock-chips.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: core: Introduce host claiming by context</title>
<updated>2017-10-30T10:45:49+00:00</updated>
<author>
<name>Adrian Hunter</name>
<email>adrian.hunter@intel.com</email>
</author>
<published>2017-09-22T12:36:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=6c0cedd1ef9527ef13e66875746570e76a3188a7'/>
<id>urn:sha1:6c0cedd1ef9527ef13e66875746570e76a3188a7</id>
<content type='text'>
Currently the host can be claimed by a task.  Change this so that the host
can be claimed by a context that may or may not be a task.  This provides
for the host to be claimed by a block driver queue to support blk-mq, while
maintaining compatibility with the existing use of mmc_claim_host().

Signed-off-by: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: core: correct taac parameter according to the specification</title>
<updated>2017-08-30T12:01:46+00:00</updated>
<author>
<name>Shawn Lin</name>
<email>shawn.lin@rock-chips.com</email>
</author>
<published>2017-08-02T03:12:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=4406ae215b5a1dd59d941c1323b9f40d241357ac'/>
<id>urn:sha1:4406ae215b5a1dd59d941c1323b9f40d241357ac</id>
<content type='text'>
Per the spec of JESD84-B51, section 7.3, replace tacc with taac to
fix the obvious typo.

Signed-off-by: Shawn Lin &lt;shawn.lin@rock-chips.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: core: Re-factor code for sending CID</title>
<updated>2017-06-20T08:30:45+00:00</updated>
<author>
<name>Ulf Hansson</name>
<email>ulf.hansson@linaro.org</email>
</author>
<published>2017-06-08T13:27:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=a1473732507499ec4002ad8cd33e645579d61a26'/>
<id>urn:sha1:a1473732507499ec4002ad8cd33e645579d61a26</id>
<content type='text'>
Instead of having the caller to check for SPI mode, let's leave that to
internals of mmc_send_cid(). In this way the code gets cleaner and it
becomes clear what is specific to SPI and non-SPI mode.

Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Reviewed-by: Shawn Lin &lt;shawn.lin@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>mmc: core: Delete error messages for failed memory allocations</title>
<updated>2017-06-20T08:30:21+00:00</updated>
<author>
<name>Markus Elfring</name>
<email>elfring@users.sourceforge.net</email>
</author>
<published>2017-05-19T11:15:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=e1df7ae30b430a3183d2a0a9b3e0b802f9d5ff49'/>
<id>urn:sha1:e1df7ae30b430a3183d2a0a9b3e0b802f9d5ff49</id>
<content type='text'>
Omit an extra message for memory allocation failures.

This issue was detected by using the Coccinelle software.

Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf
Signed-off-by: Markus Elfring &lt;elfring@users.sourceforge.net&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: core: add proper be32 annotation</title>
<updated>2017-04-24T19:42:19+00:00</updated>
<author>
<name>Winkler, Tomas</name>
<email>tomas.winkler@intel.com</email>
</author>
<published>2017-04-02T20:56:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=06c9ccb78e68e2e9b69e736fc0a39fb13be49b74'/>
<id>urn:sha1:06c9ccb78e68e2e9b69e736fc0a39fb13be49b74</id>
<content type='text'>
Annotate big endian values correctly and make sparse happy.
In mmc_app_send_scr remove scr function parameter as it was
updating card-&gt;raw_scr anyway.

Signed-off-by: Tomas Winkler &lt;tomas.winkler@intel.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
</feed>
