BMC/Intel-BMC/linux.git/drivers/media/platform/xilinx, branch dev

[media] v4l: xilinx: harmless buffer overflow

2015-05-13T19:26:48+00:00

My static checker warns that the name of the port can be 15 characters when you consider the NUL terminator and that's one more than the 14 characters in name[]. Maybe it's an off-by-one? It's unlikely that we hit the limit and even if we do the overflow will only affect one of the two bytes of padding so it's harmless. Still let's fix it and also change the sprintf() to snprintf(). Signed-off-by: Dan Carpenter Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab

[media] v4l: xilinx: VIDEO_XILINX should depend on HAS_DMA

2015-05-01T10:10:09+00:00

If NO_DMA=y: warning: (VIDEO_XILINX && VIDEO_DM365_VPFE && VIDEO_DT3155 && VIDEO_OMAP4) selects VIDEOBUF2_DMA_CONTIG which has unmet direct dependencies (MEDIA_SUPPORT && HAS_DMA) media/v4l2-core/videobuf2-dma-contig.c: In function ‘vb2_dc_mmap’: media/v4l2-core/videobuf2-dma-contig.c:207: error: implicit declaration of function ‘dma_mmap_coherent’ media/v4l2-core/videobuf2-dma-contig.c: In function ‘vb2_dc_get_base_sgt’: media/v4l2-core/videobuf2-dma-contig.c:390: error: implicit declaration of function ‘dma_get_sgtable’ VIDEO_XILINX selects VIDEOBUF2_DMA_CONTIG, which bypasses its dependency on HAS_DMA. Make VIDEO_XILINX depend on HAS_DMA to fix this. Signed-off-by: Geert Uytterhoeven Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab

v4l: xilinx: fix for include file movement

2015-04-26T16:56:08+00:00

Signed-off-by: Stephen Rothwell Signed-off-by: Linus Torvalds

[media] v4l: xilinx: Add Test Pattern Generator driver

2015-04-03T04:04:18+00:00

The TPG generates multiple static or dynamic test patterns. The driver currently hardcodes the pattern to the moving box pattern. Signed-off-by: Christian Kohn Signed-off-by: Hyun Kwon Signed-off-by: Laurent Pinchart Signed-off-by: Michal Simek Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab

[media] v4l: xilinx: Add Video Timing Controller driver

2015-04-03T04:01:37+00:00

The Video Timing Controller (VTC) includes a timing detector and/or a timing generator. Only the generator is currently supported. Signed-off-by: Laurent Pinchart Signed-off-by: Michal Simek Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab

[media] v4l: xilinx: Add Xilinx Video IP core

2015-04-03T03:59:49+00:00

Xilinx platforms have no hardwired video capture or video processing interface. Users create capture and memory to memory processing pipelines in the FPGA fabric to suit their particular needs, by instantiating video IP cores from a large library. The Xilinx Video IP core is a framework that models a video pipeline described in the device tree and expose the pipeline to userspace through the media controller and V4L2 APIs. Signed-off-by: Laurent Pinchart Signed-off-by: Hyun Kwon Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab